Abstract: A video transcoder for converting an encoded input video bit-stream having one spatial resolution into an encoded output video bit-stream having a lower spatial resolution, wherein learned statistics of intra-mode transcoding are used to constrain the search of intra modes for the output video bit-stream. The statistics of intra-mode transcoding can be gathered, e.g., by applying brute-force downsizing to a training set of video frames and then analyzing the observed intra-mode transcoding patterns to determine a transition-probability matrix for use during normal operation of the transcoder. The transition-probability matrix enables the transcoder to select appropriate intra modes for the output video bit-stream without performing a corresponding exhaustive full search, which advantageously reduces the computational complexity and processor load compared to those of a comparably performing prior-art video transcoder.

Abstract: Various embodiments of the present invention provide systems and methods for data storage. As an example, storage devices are disclosed that include a plurality of memory blocks, an unreliable block identification circuit, and a partial failure indication circuit. Each of the plurality of memory blocks includes a plurality of memory cells that decrease in reliability over time as they are accessed. The unreliable block identification circuit is operable to determine that one or more of the plurality of memory blocks is unreliable, and the partial failure indication circuit is operable to disallow write access to the plurality of memory blocks upon determination that an insufficient number of the plurality of memory blocks remain reliable.

Abstract: Methods and structure described herein provide for reducing the overall delay of an RS encoder/decoder without changing the essential functionality of the RS encoder/decoder. In one embodiment, a cascade module reduces the combinatorial logical delay by reducing the total number of logical devices. In doing so, the cascade module couples encoder/decoder slices into blocks. A first block of the encoder/decoder slices is selectively operable in parallel with a second block of encoder/decoder slices. The number of encoder/decoder blocks is less than the overall number of encoder/decoder slices. The cascade module may also include a switch that selects encoder/decoder slices as needed, thereby providing for the implementation of the RS encoder/decoder with fewer logical devices.

Abstract: A method for editing a title recorded on a digital storage medium. The method includes the steps of (A) defining a portion of the title to be edited for slow or fast motion playback, (B) modifying at least one address of presentation control information (PCI) for the title based upon a user editing command and (C) controlling playback of the title in accordance with the modified PCI to carry out the user editing command.

Abstract: A method of deblocking an input signal is disclosed. The method generally includes the steps of (A) calculating a plurality of transform coefficients corresponding to each of a plurality of blocks in the input signal at baseband, (B) calculating a plurality of quantization parameters based on the transform coefficients, at least one of the quantization parameters corresponding to each respective one of the blocks and (C) generating an output signal by deblocking the input signal based on the quantization parameters.

Abstract: A parity checking circuit which includes a microprocessor, instruction memory, a parity checker, an address capture device, a data bus connected to the microprocessor, the instruction memory and the parity checker, and an address bus connected to the microprocessor, the instruction memory and the address capture device. The instruction memory sends a parity bit to the parity checker, and the parity checker compare an address it receives from the address bus to the parity bit it receives from the instruction memory. If a parity error is detected, an error signal is sent to the address capture device and the address capture device captures the address for subsequent storage in a storage device, such as flash memory. The circuit also includes registers and a watchdog reset device which facilitates a system level reset at the command of the microprocessor.

Abstract: Disclosed is a method of detecting an access to de-allocated memory, comprising: creating a pool of fixed size memory blocks that are a non-zero integer multiple of a page size of a processor; receiving a request for an allocation of a block of memory; recording a set of allocation context information in a fixed size memory block; returning a pointer to an allocation of memory within said fixed size memory block; receiving a request to de-allocate said block of memory; recording a set of de-allocation context information in said fixed size memory block; and, setting an indicator in a page table entry associated with said fixed size memory block to a first value that indicates access to said fixed size memory block is not allowed.

Abstract: In one embodiment, a storage-device-implemented method for estimating one or more channel parameters of a storage device including a read channel and a storage medium with a bit sequence stored on the storage medium. The method includes: (a) the storage device reading at least a portion of the bit sequence from the storage medium to generate a bit response; (b) the storage device convolving the bit response to compute an impulse response of the read channel; and (c) the storage device estimating one or more channel parameters based on the computed impulse response.

Abstract: The present invention is directed to methods for disabling unused IO resources in a platform-based integrated circuit. A slice is received from a vendor. The slice includes an IO circuit unused by a customer. The IO circuit is disabled. For example, when the IO circuit is desired to be tied to a power source, a primary input/output pin of the IO circuit is shorted to a power bus of the IO circuit. When the IO circuit is desired to be tied to a ground source, a primary input/output pin of the IO circuit is shorted to a ground bus of the IO circuit. When the IO circuit is desired to be left floated, a primary input/output pin of the IO circuit is not connected to any bonding pad cell of the slice. Next, the IO circuit is removed from the customer's logic design netlist. The IO circuit is inserted in the vendor's physical design database.

Abstract: A configurable low-density parity check code (LDPC) decoder and a method of configuring the decoder. In one embodiment, the configurable LDPC decoder includes: (1) pluralities of parity check units and bit node units, (2) direct and reverse multi-size barrel shifters coupled to the pluralities of parity check units and bit node units and (3) a control circuit, coupled to the pluralities of parity check units and bit node units and the direct and reverse multi-size barrel shifters and configured to configure sizes of the direct and reverse multi-size barrel shifters and numbers of the pluralities of parity check units and bit node units to cooperate therewith based on a block size of a particular LDPC code.

Abstract: A method of motion estimation (ME) refinement. The method generally includes the steps of (A) generating an initial motion vector (MV) by conducting a first ME on an initial block in a picture, the initial block covering an initial area of the picture, (B) generating a current MV by conducting a second ME on a current block in the picture, (i) the current block covering a subset of the initial area and (ii) the second ME being seeded by the initial MV, (C) generating at least one additional MV by conducting at least one third ME on the current block, the at least one third ME being seeded respectively by at least one neighboring MV spatially adjacent to the current MV and (D) generating a refined MV of the current block by storing in a memory a best among the current MV and the additional MV.

Abstract: Securely storing data to an optical disc has been described, including generating write data that includes the data and overhead data that facilitates reading the data from the disc; and configuring the overhead data according to a key.

Abstract: A system for, and method of, assigning code blocks to constituent decoding units in a turbo decoding system having parallel decoding units. In one embodiment, the method includes: (1) representing the turbo decoding system as a resource diagram rectangle, (2) representing the code blocks as code block rectangles, (3) mapping the code block rectangles into the resource diagram rectangle and (4) assigning the code blocks to the constituent decoding units based on the mapping.

Abstract: A method includes generating trace data at a device associated with data communication to and from a computer storage device through an appropriate communication link therefor and transmitting the trace data through the appropriate communication link. The trace data is configured to enable debugging of a set of instructions associated with the device. The method also includes capturing the trace data transmitted through the appropriate communication link through a protocol analyzer, a host system or the protocol analyzer coupled to the host system and analyzing the trace data therein to obtain information associated with the set of instructions associated with the device. The protocol analyzer, the host system or the protocol analyzer coupled to the host system is configured to be external to the device associated with the data communication to and from the computer storage device.

Abstract: In one embodiment, a communications system has a write path and a read path. In the write path, a local/global interleaver interleaves a user data stream, and an error-correction (EC) encoder encodes the user data stream to generate an EC codeword. A local/global de-interleaver de-interleaves the parity bits of the EC codeword, and both the original un-interleaved user data and the de-interleaved parity bits are transmitted via a noisy channel. In the read path, a channel detector recovers channel soft-output values corresponding to the codeword. A local/global interleaver interleaves the channel values, and an EC decoder decodes the interleaved values to recover the original codeword generated in the write path. A de-multiplexer de-multiplexes the user data from the parity bits. Then, a local/global de-interleaver de-interleaves the user data to obtain the original sequence of user data that was originally received at the write path.

Abstract: A method for transcoding from an H.264 format to an MPEG-2 format is disclosed. The method generally comprises the steps of (A) decoding an input video stream in the H.264 format to generate a picture having a plurality of macroblock pairs that used an H.264 macroblock adaptive field/frame coding; (B) determining a mode indicator for each of the macroblock pairs; and (C) coding the macroblock pairs into an output video stream in the MPEG-2 format using one of (i) an MPEG-2 field mode coding and (ii) an MPEG-2 frame mode coding as determined from the mode indicators.

Abstract: A method and system for storing excess data in a redundant array of independent disks (RAID) level 6 are disclosed. In one embodiment, a method for storing excess data in a RAID 6 volume includes writing excess data to Q parity blocks of a first RAID 6 volume when a receipt of the excess data directed to the first RAID 6 volume is detected subsequent to a saturation of the first RAID 6 volume, where the first RAID 6 volume is converted to a pseudo-RAID 5 volume with P parity blocks. The method further includes re-computing the P parity blocks of the pseudo-RAID 5 volume based on data blocks of the pseudo-RAID 5 volume. In addition, the method includes constructing a second RAID 6 volume based on the pseudo-RAID 5 volume when at least one additional drive is inserted to the pseudo-RAID 5 volume.

Abstract: A method for metadata management in a storage system may include providing a metadata queue of a maximum size; determining whether the metadata for a particular sub-LUN is held in the metadata queue; updating the metadata for the particular sub-LUN when the metadata for the particular sub-LUN is held in the metadata queue; inserting the metadata for the particular sub-LUN at the head of the metadata queue when the metadata queue is not full and the metadata is not held in the metadata queue; replacing an entry in the metadata queue with the metadata for the particular sub-LUN and moving the metadata to the head of the metadata queue when the metadata queue is full and the metadata is not held in the metadata queue; and controlling the number of sub-LUNs in the storage system to manage data accessed with respect to an amount of available data storage.

Abstract: A method for metadata management in a storage system configured for supporting sub-LUN tiering. The method may comprise providing a metadata queue of a specific size; determining whether the metadata for a particular sub-LUN is cached in the metadata queue; updating the metadata for the particular sub-LUN when the metadata for the particular sub-LUN is cached in the metadata queue; inserting the metadata for the particular sub-LUN to the metadata queue when the metadata queue is not full and the metadata is not cached; replacing an entry in the metadata queue with the metadata for the particular sub-LUN when the metadata queue is full and the metadata is not cached; and identifying at least one frequently accessed sub-LUN for moving to a higher performing tier in the storage system, the at least one frequently accessed sub-LUN being identified based on the metadata cached in the metadata queue.