Abstract: Methods and systems for communication between two storage controllers. A first storage controller specifies a special frame indicator in a frame of a protocol that is also used by a first storage controller to send a storage command to a storage device. The first storage controller transmits the frame to a second storage controller such that the frame comprises data in a payload field of the frame.

Abstract: A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of an IO receiver, and controllably generating a second bias voltage from an external voltage supplied through an IO pad to be within the upper tolerable limit of the operating voltage of the IO receiver. The method also includes deriving an output voltage from the first bias voltage during a normal condition and a tolerant condition, and deriving the output voltage from the second bias voltage during a failsafe condition. The tolerant condition is a mode of operation where the external voltage supplied through the IO pad varies from zero to a value higher than the supply voltage, and the failsafe condition is a mode of operation where the supply voltage is zero.

Abstract: A routing multiplexer system provides p outputs based on a selected permutation of p inputs. Each of a plurality of modules has two inputs, two outputs and a control input and is arranged to supply signals at the two inputs to the two outputs in a direct or transposed order based on a value of a bit at the control input. A first p/2 group of the modules are coupled to the n inputs and a second p/2 group of the modules provide the n outputs. A plurality of control bit tables each contains a plurality of bits in an arrangement based on a respective permutation. The memory is responsive to a selected permutation to supply bits to the respective modules based on respective bit values of a respective control bit table, thereby establishing a selected and programmable permutation of the inputs to the outputs.

Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the ground plane used to ground the low speed circuitry of the package.

Abstract: A method, an apparatus and/or a system to regulate yellow traffic in a network is provided. In one embodiment, the method includes quantifying, an extent of violation of a transmission rate of a data traffic relative to a committed bandwidth profile in a network. The data traffic is generated through a client device coupled to the network. The method also includes regulating, a volume of the data traffic associated with a particular level of compliance relative to the committed bandwidth profile, at an edge node of the network, based on the quantification. The committed bandwidth profile specifies an average rate of committed and excess data traffic generated by the client device. The particular level of compliance is characterized by the transmission rate exceeding a committed information rate and lying within a peak information rate. The peak information rate is maximum allowable rate of admission of frames into the network.

Abstract: A video transcoder for converting a compressed input video bit-stream having one spatial resolution into a compressed output video bit-stream having a different spatial resolution using a plurality of resizing channels. The transcoder has a kernel that partially decodes the compressed input video bit-stream to generate partially decoded video data. The data segments corresponding to picture portions that have both intra- and inter-predicted blocks in close spatial proximity to one another are applied to a mixed-mode resizing channel that is specifically designed for processing such data segments. For each received data segment, the control logic of the channel selects, from a bank of pre-configured resizers, a resizer that is deemed to be most suitable for resizing the image portion represented by that data segment in a computationally efficient manner. The data segment is processed in the selected resizer to generate the corresponding resized-image data.

Abstract: Methods and apparatus for improved performance in communications between a SAS/STP initiator device and a plurality of SATA storage devices coupled with the initiator through an enhanced switching device. The switching device is enhanced in accordance with features and aspects hereof to receive a DMA SETUP FIS from a SATA storage device and to transmit multiple modified DMA SETUP FISs to the initiator where each modified DMA SETUP FIS comprises a subcount less than the maximum count in the received DMA SETUP FIS.

Abstract: A video transcoder for converting a compressed input video bit-stream having one spatial resolution into a compressed output video bit-stream having a different spatial resolution in a manner that enables the transcoder to dynamically change the amount of computational resources allocated to the conversion process. In one embodiment, the video transcoder has a plurality of configurable processing paths whose configuration determines the amount of allocated computational resources. Exemplary processing-path configuration changes may include, but are not limited to engaging or disengaging a processing path, redirecting a data flow from flowing through one processing path to flowing through another processing path, and attaching or detaching one or more processing modules to an engaged processing path.

Abstract: Methods and apparatus for improved performance in communications with a SATA target device. Features and aspects hereof provide for continuing DMA transfers from a storage controller (e.g., a SATA host or a SAS/STP initiator) to a SATA target device without regard to receipt of DMA ACTIVATE Frame Information Structures (FIS). Logic to implement these features may be provided by bridge logic within an enhanced SAS expander coupled with an enhanced SAS/STP initiator or may be provided by suitable logic in an enhanced SATA host coupled directly with an enhanced SATA target device. By continuing DMA transfer of data from the initiator/host to the SATA target device without regard to receipt of a DMA ACTIVATE FIS, more of the available bandwidth of the SAS/SATA communication link may be utilized. Other standard features of the SAS/SATA protocols provide for flow control to prevent overrun of the SATA target device's buffers.

Abstract: In one embodiment, a method of reclaiming data storage in a storage device slated as a reclamation target is disclosed. The method includes generating a first list of one or more portions of storage from the reclamation target that each possesses an application programming interface (API) state of unused per a system that uses the storage device. The method also includes identifying in the reclamation target, a reclamation state for each portion of storage from the first list. The method further includes comparing the API state and the reclamation state for each portion of storage in the first list. In addition, the method includes identifying a first subset of portions of storage from the first list as having a mismatched state. The method further includes converting the reclamation state of each of the portion of storage in the first subset from the used state to a marked for reclamation state.

Abstract: Methods of designing an IC and an apparatus are disclosed. In one embodiment, a method includes: (1) creating a functional circuit for a functional block of an IC design, (2) verifying said functional circuit satisfies a rule-set for said IC design, wherein said rule-set is context-based with respect to said design flow, (3) synthesizing a logical circuit based on the functional circuit; (4) verifying the logical circuit satisfies the rule set; (5) implementing a physical layout of the logical circuit; and (6) verifying the physical layout satisfies the rule set, wherein each step of the method is carried out by at least one EDA tool.

Abstract: An apparatus and method for providing a read-only memory (ROM) bit cell having one each of a PMOS transistor and an NMOS transistor, which has reduced static and dynamic electric power losses, are described. In particular, the bit cell does not require a pre-charge transistor. The sense amplifier for determining the voltages on ROM bit lines may be a digital inverter, address decoding may be simplified since there are no timing requirements with respect to transistor pre-charge, and chips containing a plurality of ROM bit cell may be readily programmed. In one embodiment of the invention, each bit cell includes one PMOS transistor having its source in electrical connection with a voltage source, its drain connected or unconnected to a bit line, and its gate connected to an inverted version of the word line signal; and one NMOS transistor having its source connected to a lower voltage source, its drain connected or disconnected to the bit line, and its gate connected to the word line.

Abstract: A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of one or more constituent active circuit element(s) of an Input/Output (IO) core device of an integrated circuit (IC) to be interfaced with an IO pad, and controllably generating a second bias voltage from an external voltage supplied through the IO pad to be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element(s) of the IO core device to be interfaced with the IO pad. The method also includes controllably utilizing a control signal generated by the IO core to derive an output bias voltage from the first bias voltage during a driver mode of operation or the second bias voltage during a failsafe mode of operation and a tolerant mode of operation.

Abstract: Disclosed is a method of controlling power. Multiple paths via multiple I/O ports couple a server to a storage array. When I/O loads are low, it is determined if an I/O port may be deactivated and placed in a power saving mode. An I/O port may not be deactivated if deactivating that I/O port will affect a high-availability requirement or a performance requirement. Requests are stopped from being sent to an I/O port to be deactivated. When the port to be deactivated becomes idle, the I/O port is placed in a power saving mode. When I/O loads increase to a point where it is necessary to reactivate the I/O port, the I/O port is activated.

Abstract: A semiconductor device includes a semiconductor die mounted over a package substrate. The die has a bond pad located thereover. A stud bump consisting substantially of a first metal is located on the bond pad. A wire consisting substantially of a different second metal is bonded to the stud bump.

Abstract: Disclosed is a method of improving storage reliability comprising receiving an indicator of an impending failure of a first storage device in a RAID group. In response to the indicator, writing data to the first storage device is ceased. A first block of data directed to be written on the first storage device is written to a memory device. Data stored on the first storage device is copied to a second storage device. The first block of data is copied from the memory device to the second storage device. The RAID group is operated with the second storage device functioning in place of the first storage device. Data is read from said second storage device.

Abstract: In described embodiments, automatic de-emphasis setting is provided for driving a capacitive backplane. Line impedance and line length of a transmission (TX) device are measured that form a load impedance of a driver. For some exemplary embodiments, the line impedance is predominantly a line capacitance, and such embodiments detect this capacitance. Measured line impedance is converted to a control signal (such as, for example, a three bit digital control signal) which automatically sets the de-emphasis of the TX stage. With the amount of capacitance and the length of the transmission line, the appropriate de-emphasis settings might be determined, and such de-emphasis setting be applied by the transmitter to the driver to compensate for transmission line effects.

Abstract: An application programming interface (API) implementation that can interface between an application and a programming library. The implementation includes a Function Router Wrapper that receives a formatted string from the application. The formatted string includes a function name element filled with a function name, an input element filled with function input parameters, and an unfilled output element. The Function Router Wrapper converts the formatted string and passes it to a Function Router, which parses the converted formatted string to access the function name and the function input parameters. The Function Router calls a library function based on the accessed information. When the called library function is completed, the Function Router collects generated function outputs and embeds them into the formatted string output element. The Function Router passes the formatted string back up to the Function Router Wrapper, which converts the formatted string and passes it back up to the application.

Abstract: An apparatus comprising a voltage controlled oscillator, a first charge pump, a second charge pump, a switch circuit and a comparator circuit. The voltage controlled oscillator may be configured to generate an output signal oscillating at a first frequency in response to a control signal. The charge pump circuit may be configured to generate a first component of the control signal in response to a first adjustment signal and a second adjustment signal. The second charge pump may be configured to generate a second component of the control signal in response to a first intermediate signal and a second intermediate signal. The switch circuit may be configured to generate the first intermediate signal and the second intermediate signal in response to the first adjustment signal and the second adjustment signal. The comparator circuit may be configured to generate the first and second adjustment signals in response to a comparison between (i) an input signal having a second frequency and (ii) the output signal.

Abstract: Methods for establishing benchmarks and for analyzing benefits associated with voltage scaling are provided. In one embodiment, the method for establishing benchmarks includes: (1) synthesizing a netlist from a RTL of a functional IC design; (2) implementing a layout of an IC from the netlist, wherein the synthesizing and the implementing are performed at designated voltages and frequencies over a voltage and a frequency range, the voltage range including a voltage scaling range and a voltage associated with a designated implementation of the IC; (3) obtaining measurements of at least one voltage scaling metric associated with the IC at each of the designated voltages and frequencies; and (4) normalizing measurements associated with the voltage scaling range to measurements associated with the designated implementation employing a processor to obtain normalized benchmarks for analyzing optimization of the IC associated with voltage scaling. EDA tools may be used for synthesizing, implementing and obtaining.