Abstract: A method incorporating adaptive body biasing into an integrated circuit design flow includes the steps of (A) adding adaptive body biasing input/outputs (I/Os) during a bonding layout stage of the integrated circuit design flow, (B) floorplanning the integrated circuit design, (C) generating an adaptive body biasing mesh and (D) generating a layout of the integrated circuit design based upon a plurality of adaptive body biasing corners.

Abstract: In one embodiment, a storage-device-implemented method for estimating one or more channel parameters of a storage device including a read channel and a storage medium with a bit sequence stored on the storage medium. The method includes: (a) the storage device reading at least a portion of the bit sequence from the storage medium to generate a bit response; (b) the storage device convolving the bit response to compute an impulse response of the read channel; and (c) the storage device estimating one or more channel parameters based on the computed impulse response.

Abstract: Apparatus and methods for translation of data formats between multiple interface types. Translation logic is interposed between a producer circuit and a consumer circuit to translate data formats of data signals generated by the producer for application to the consumer. The translation logic may include multiple translators to provide translations between any of multiple producer data formats and any of multiple consumer data formats. One or more producer circuits may thus be selectively coupled with one or more consumer circuits through the translation logic circuit.

Abstract: A method of manufacturing a flip-chip package and a flip-chip package manufactured by such method. In one embodiment, the method includes: (1) mounting a die to a first die, (2) encapsulating the second die with a molding compound and (3) selectively ablating the molding compound based on an expected heat generation of portions of the second die to reduce a thickness of the molding compound proximate the portions.

Abstract: An electronic device includes an integrated circuit and a heat spreader. The integrated circuit includes a substrate with an active via located therein. The heat spreader includes a thermally conductive core. The active via is connected to a corresponding heat spreader via that passes through the thermally conductive core.

Abstract: An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.

Abstract: An electronic device bond pad includes an Al layer located over an electronic device substrate. The Al layer includes an intrinsic group 10 metal located therein.

Abstract: An apparatus generally having a first circuit and a second circuit. The first circuit may be configured to (i) generate an equalizer parameter in response to an input signal, the equalizer parameter causing a cancellation of post-cursor inter-symbol interference from a plurality of symbols in the input signal and (ii) generate an output signal in response to both the input signal and the equalizer parameter. The second circuit may be configured to (i) generate a target parameter signal in response to the input signal, the target parameter signal representing a mean value of a plurality of sample points of the symbols and (ii) generate a control signal in response to the target parameter signal, the control signal causing a reduction of the equalizer parameter, the reduction causing a decrease in the cancellation of the post-cursor inter-symbol interference from the symbols, wherein the apparatus does not cancel pre-cursor inter-symbol interference.

Abstract: The present invention is directed to an architecture for promoting improved cloud computing. The architecture includes a plurality of diskless server nodes. The architecture further includes a plurality of Serial Attached Small Computer System Interface (SAS) switches, the plurality of SAS switches being connected to the plurality of diskless server nodes. The architecture further includes a storage system, the storage system configured for being communicatively coupled to the plurality of servers via the plurality of SAS switches. Further, the storage system is configured for implementing Controlled Replication Under Scalable Hashing (CRUSH) redundancy. Still further, the architecture is configured for dynamically mapping data stores of the storage system to the diskless server nodes.

Abstract: An apparatus and a method of generating a flexible ramptime limit for an electronic circuit, a computer program product that performs the same method, and a method of manufacturing an electronic circuit employing a flexible ramptime limit is disclosed. In one embodiment, the method for generating a flexible ramptime limit includes: (1) calculating a frequency based ramptime limit for the electronic circuit, (2) obtaining a library based ramptime limit for the electronic circuit, (3) determining a minimum ramptime limit between the frequency based ramptime limit and the library based ramptime limit and (4) selecting the minimum ramptime limit as the flexible ramptime limit.

Abstract: In one embodiment, a de-interleaver receives soft-output values corresponding to bits of an LDPC-encoded codeword. The de-interleaver has scratch pad memory that provides sets of the soft-output values to a local de-interleaver. The number of values in each set equals the number of columns in a block column of the LDPC H-matrix. Each set has at least two subsets of soft-output values corresponding to at least two different block columns of the LDPC H-matrix, where the individual soft-output values of the at least two subsets are interleaved with one another. Local de-interleaving is performed on each set such that the soft-output values of each subset are grouped together. Global de-interleaving is then performed on the subsets such that the subsets corresponding to the same block columns of the H-matrix are arranged together. In another embodiment, an interleaver performs global then local interleaving to perform the inverse of the de-interleaver processing.

Abstract: Contentual metadata of an extended cache is stored within the extended cache. The contentual metadata of the extended cache is approximated utilizing a counting Bloom filter. The counting Bloom filter is stored within a primary cache. Contentual metadata of the primary cache is stored within the primary cache. One of a data read or a data write is executed without accessing the contentual metadata of the extended cache stored within the extended cache.

Abstract: A device for placing one or more sutures through a section of tissue, especially a section of thick and/or moving tissue such as the wall of a beating heart. The device includes a tissue welting tip having a trough for forming a welt in a tissue section, an alignment guide pivotally mounted in the distal end adjacent to the trough, and having an opening receiving a guide wire and an elongated sleeve slidably engagable with the guide wire there through. The device also includes one or more expandable tissue engaging member(s) on the sleeve selectively expandable from a collapsed configuration having a diameter small enough to pass through the opening in the tip to an expanded configuration having a diameter large enough to engage a tissue section and urge it into the trough to form a welt in the tissue section and a retractable needle extendable through at least two portions of a tissue section while the tissue section is engaged with the trough.

Abstract: A method for abating effluent from an etching process in one embodiment includes advancing etch gas product into a passageway of a gas connector in direct fluid communication with a first chamber of an interior void of an apparatus, advancing a gas from a gas source into said passageway of said gas connector at the same time said etch gas product is being advanced into said passageway, and advancing humidified gas from a humidified gas source into a second chamber of said interior void.

Abstract: A circuit generally having a first module, a second module and a third module is disclosed. The first module may be configured to (i) generate a plurality of parsed residual blocks by parsing an 8×8 CABAC (context-based adaptive binary arithmetic coding) residual block received in an input signal and (ii) generate a plurality of metric signals resulting from the parsing of the 8×8 CABAC residual block. The second module may be configured to generate a scanning position signal based on the metric signals. The third module may be configured to generating a plurality of 4×4 CAVLC (context-based adaptive variable length coding) residual blocks in an output signal by sub-sampling the parsed residual blocks based on the scanning position signal.

Abstract: A method of operation for an input/output assignment tool is disclosed. The method generally includes the steps of (A) generating a graphic presentation to a user displaying (i) a circuit icon having a plurality of pin icons and (ii) a plurality of signal icons, (B) moving a first of the signal icons within the graphic presentation to a first of the pin icons in response to a move command from the user and (C) indicating an acceptance of an association between the first signal icon and the first pin icon in response to the association passing a rule.

Abstract: A method, system and apparatus of shared bus architecture are disclosed. In one embodiment, a method controlling set of multiplexers using an arbiter circuit per transaction, selecting one of a memory clock and a host clock based on an arbitration status, driving a final output on an interface to provide glitchless switching of an interface signal, connecting the interface signal to a tri-state buffer, and setting the direction of a data and address bus based on the connection of the interface signal to the tri-state buffer. The method may include applying a fair arbitration policy to ensure that none of the devices coupled to the interface signal and application threads running on processor requiring data from different devices are starved.

Abstract: An apparatus comprising a test termination card having a first set of connections and a second set of connections. The first set of connections may be configured to connect to a specific pinout of a device under test. The second set of connections may be configured to connect to a general pinout of a tester load board. The termination card may toggle between (a) connecting the first set of connectors to the second set of connectors to implement a first test type and (b) disconnecting the first set of connectors from the second set of connectors to implement a second test type.

Abstract: A methods of characterizing a regular electronic circuit and using a parameterized model of an electronic circuit to create a model for another electronic circuit. In one embodiment, the method of characterizing includes: (1) characterizing fewer than all sub-circuits associated with input and output pins of the circuit to yield data regarding the sub-circuits, (2) generating a data file containing the data, the data file constituting an expandable parameterized model of the circuit.

Abstract: A method of designing an integrated circuit, an EDA tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method includes: (1) generating a set of constraint equations representing clock-insertion delay values for the integrated circuit as variables, (2) determining bounds on each of the clock-insertion delay values based on the constraint equations and (3) generating a set of closing commands based on the bounds for driving a design of the integrated circuit to closure, wherein each step of the method is carried out by at least one EDA tool.