Abstract: In one embodiment, a multi-mode Advanced Encryption Standard (MM-AES) module for a storage controller is adapted to perform interleaved processing of multiple data streams, i.e., concurrently encrypt and/or decrypt string-data blocks from multiple data streams using, for each data stream, a corresponding cipher mode that is any one of a plurality of AES cipher modes. The MM-AES module receives a string-data block with (a) a corresponding key identifier that identifies the corresponding module-cached key and (b) a corresponding control command that indicates to the MM-AES module what AES-mode-related processing steps to perform on the data block. The MM-AES module generates, updates, and caches masks to preserve inter-block information and allow the interleaved processing. The MM-AES module uses an unrolled and pipelined architecture where each processed data block moves through its processing pipeline in step with correspondingly moving key, auxiliary data, and instructions in parallel pipelines.

Abstract: Methods and apparatus for cut-through cache memory management in write command processing on a mirrored virtual volume of a virtualized storage system, the virtual volume comprising a plurality of physical storage devices coupled with the storage system. Features and aspects hereof within the storage system provide for receipt of a write command and associated write data from an attached host. Using a cut-through cache technique, the write data is stored in a cache memory and transmitted to a first of the plurality of storage devices as the write data is stored in the cache memory thus eliminating one read-back of the write data for transfer to a first physical storage device. Following receipt of the write data and storage in the cache memory, the write data is transmitted from the cache memory to the other physical storage devices.

Abstract: A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.

Abstract: A RAID level migration system and method are provided that enable RAID level migration to be performed without the use of a hardware RAID controller with NVRAM for storing the migration parameters. Eliminating the need for a hardware controller having NVRAM significantly reduces the costs associated with performing RAID level migration. The system and method are capable of migrating from any arbitrary RAID level to any other arbitrary RAID level.

Abstract: The present invention is a method for providing address decode and Virtual Function (VF) migration support in a Peripheral Component Interconnect Express (PCIE) multi-root Input/Output Virtualization (IOV) environment. The method may include receiving a Transaction Layer Packet (TLP) from the PCIE multi-root IOV environment. The method may further include comparing a destination address of the TLP with a plurality of base address values stored in a Content Addressable Memory (CAM), each base address value being associated with a Virtual Function (VF), each VF being associated with a Physical Function (PF). The method may further include when a base address value included in the plurality of base address values matches the destination address of the TLP, providing the matching base address value to the PCIE multi-root IOV environment by outputting from the CAM the matching base address value.

Abstract: The design of integrated circuits, i.e., semiconductor products, is made easier with a semiconductor platform having versatile power mesh that is capable of supporting simultaneous operations having different frequencies on the semiconductor product; e.g., higher frequency operations may be embedded as diffused blocks within the lower layers or may be programmed from a configurable transistor fabric above the diffused layers. Preferably the power mesh is located above the layers having the operations requiring the different frequencies, and may be fixed in an application set given to a chip designer or may be configurable by the designer her/himself. For example, to support high speed communications adjacent an embedded high speed data transceiver, the transistor fabric may be programmed as a data link layer having higher performance requirements than the rest of the integrated circuit.

Abstract: A method for recovering solid state drive (SSD) data may comprise: detecting a failed SSD comprising one or more data blocks; receiving a request to write data to the one or more data blocks of the failed SSD; writing the data to one or more data blocks of an operational drive; and rebuilding the failed SSD from the failed SSD and the one or more data blocks of the operational drive. A system for recovering solid state drive (SSD) data may comprise: means for detecting a failed SSD comprising one or more data blocks; means for receiving a request to write data to the one or more data blocks of the failed SSD; means for writing the data to one or more data blocks of an operational drive; and means for rebuilding the failed SSD from the failed SSD and the one or more data blocks of the operational drive.

Abstract: An electronic pressure-sensing device 100 comprising a transistor 105 located on a substrate 110. The device also comprises a linker arm 115 that has a tip 120 which is configured to touch a contact region 125 of the substrate that is near the transistor. The device also comprises a pressure converter 130 that is mechanically coupled to the linker arm. The pressure converter is configured to cause, in response to a pressure change, the tip to impart a force capable of changing an electrical conductivity of the transistor.

Abstract: The present invention is a method for handling an operation system kernel-provided command via a software-based device driver. The method includes receiving the operation system kernel-provided command from an operation system kernel. The method further includes determining if a kernel virtual address is required for responding to the command. The method further includes initiating a Direct Memory Access (DMA) operation for providing data to the operating system kernel in response to the command when a kernel virtual address is not required for responding to the command. The method further includes allocating a device driver buffer with a DMA address and a virtual address when a kernel virtual address is required for responding to the command.

Abstract: A system and method of a skip based control logic for a first in first out (FIFO) buffer is disclosed. In one embodiment, a FIFO buffer system includes a storage for storing data, a write pointer for pointing to a write address of the storage for a write operation, and a read pointer for pointing to a read address of the storage for a read operation. Further, the FIFO buffer system includes a control logic for incrementing the read pointer based on a skip parameter of a skip register. The skip parameter is used to characterize a validity of the data for the read operation.

Abstract: Lighting apparatus and structures are described to space electrical drivers from a light panel. In this way, a driver box housing the driver can be spaced from the light panel to communicate with pre-existing facilities (e.g. electrical wiring) and can serve the additional advantage of keeping the driver box out of standing water that may accumulate on the structure.

Abstract: A crimpable magnesium sleeve for securing a suture within the body and for dissolving over time while introducing only compatible amounts of magnesium into the body. An instrument for placing such a sleeve on a suture crimping the sleeve and cutting the suture after placement. An alloy of magnesium, zinc, and aluminum may be used to form the sleeve.

Abstract: In one embodiment, a hard-disk drive system performs fly-height control using a read-back mode and a loop-back mode. The read-back mode measures first and second harmonics pre-recorded on the medium and divides the first measurement by the second to obtain a read-back mode harmonic ratio. The loop-back mode measures the same first and second harmonics; however, the harmonics are provided by a write precompensation circuit rather than the medium. Further, the loop-back mode measurements are performed using asynchronous sampling to address aliasing and quantization errors. The first measurement is divided by the second to generate a loop-back harmonic ratio. In logarithm domain, the loop-back ratio is subtracted from the read-back mode ratio to remove environment-induced variations in the read path electronic circuits. The resulting harmonic ratio is subtracted from an initial harmonic ratio determined, for example, during manufacturing, to determine how much the harmonic ratio has changed.

Abstract: During the design of semiconductor products which incorporates a user specification and an application set, the application set being a partially manufactured semiconductor platform and its resources, a template engine is disclosed which uses a simplified computer language having a character whereby data used in commands identified by the character need only be input once, either by a user or by files, and that data, after it has been verified to be correct, is automatically allocated to one or more templates used to generate shells for the specification of a final semiconductor product. Data must be correct and compatible with other data before it can be used within the template engine and the generated shells; indeed the template engine cooperates with a plurality of rules and directives to verify the correctness of the data.

Abstract: A method, apparatus and system of a hierarchy of a structure of a volume is disclosed. In one embodiment, a system includes a physical volume, a structure to provide a mapping to a location of a data segment of the physical volume that may include a table having a hierarchy, a logical volume management module to define a logical volume as an arrangement of the physical volume, a snapshot module that may automatically generate a point-in-time image of the logical volume, may prompt the logical volume management module to create and insert a first table and a second table into the hierarchy of the structure, the first table may provide a set of updates to the logical volume, the second table may provide a set of updates to the point-in-time image, and a data processing system to perform a write IO (Input/Output) operation and a read IO operation.

Abstract: A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are mapped to an integrated circuit layout pattern, wherein at least one memory type comprises first and second instances that are mapped differently from one another. After mapping, at least one of the first and second instances is renamed to have a different name than the other. A post-placement model is then associated with each named memory type in the list, including a separate model for each renamed design memory.

Abstract: A method for memory management in video decoding systems that avoids some of the costs and disadvantages with video decoding systems in the prior art. Some embodiments of the present invention are especially well-suited for use with the H.264 video decoding standard. The illustrative embodiment is a memory management technique that controls which data is in the fastest memory available to a processor performing video decoding. In particular, the technique seeks to ensure that the data the processor will need is in the primary memory and expunges data that the processor will not need. The technique is based upon an analysis of predictive video decoding standards, such as H.264. By employing this technique, the illustrative embodiment ensures the expedient decoding of video frames.

Abstract: Methods and apparatus are provided for programmable decoding of a plurality of code types. A method is provided for decoding data encoded using one of a plurality of code types, where each of the code types correspond to a communication standard. The code type associated with the data is identified and the data is allocated to a plurality of programmable parallel decoders. The programmable parallel decoders can be reconfigured to decode data encoded using each of the plurality of code types. A method is also provided for interleaving data among M parallel decoders using a communications network. An interleaver table is employed, wherein each entry in the interleaver table identifies one of the M parallel decoders as a target decoder and a target address of a communications network for interleaved data. Data is interleaved by writing the data to the target address of the communications network.

Abstract: Methods and structure described herein provide for detecting data inversions between electronic devices in communication with one another and automatically correcting those that inversions. An electronic device may be configured with a receiver that is configured for receiving differential serial data from a transmitter of another electronic device. The differential serial data is formatted according to a particular communication protocol associated with the electronic devices. The receiver detects an invalid sequence in the received differential serial data, such as an inverted SAS primitive, and automatically change the receive logic of the receiver such that subsequent received differential serial data is in the proper polarity. The transmitting device does not require notification of the change in receive logic.

Abstract: A system comprising a scheduler, a first core, and a second core. The scheduler may be configured to prioritize a plurality of input/output (IO) requests. The first core may be configured to process one of the plurality of IO requests based on the prioritizing of the plurality of IO requests. The second core may be configured to process a different one of the plurality of IO requests based on the prioritizing of the plurality of IO requests.