Abstract: A memory for an integrated circuit, a method of designing a memory and an integrated circuit manufactured by the method. In one embodiment, the memory includes: (1) one of: (1a) at least one data input register block and at least one bit enable input register block and (1b) at least one data and bit enable merging block and at least one merged data register block, (2) one of: (2a) at least one address input register block and at least one binary to one-hot address decode block and (2b) at least one binary to one-hot address decode block and at least one one-hot address register block and (3) a memory array, at least one of the blocks having a timing selected to match at least some timing margins outside of the memory.

Abstract: A DMA controller and a method for statistical allocation of multichannel DMA bandwidth. In one embodiment, the DMA controller includes: (1) channel interfaces including respective counters and configured to provide request signals, priority signals and counter value signals representing current values of the counters at a given time and (2) a grant control unit coupled to the channel interfaces and configured to grant DMA access to one of the channel interfaces based on values of the priority signals and the counter value signals.

Abstract: A method and system for prefetching sound data in a sound processor system. The method includes integrating a prefetching function into at least one voice engine by, providing a setup phase, a data processing phase, and a cleanup phase, and prefetching sound data from a memory during the cleanup phase. As a result, the prefetching of sound data is optimized.

Abstract: A multi-byte cyclic redundancy check (CRC) calculation circuit and a method of calculating a multi-byte CRC. In one embodiment, the circuit includes: (1) a plurality of modules each configured to receive remainder bits in first inputs thereof and different numbers of portions of an input message in second inputs thereof and compute candidate CRC bits based thereon, (2) a storage element configured to receive output bits from one of the plurality of modules and provide the output bits to the first inputs as the remainder bits and (3) a multiplexer coupled to first outputs of the plurality of modules and configured to select from among the candidate CRC bits to yield a CRC for the input message.

Abstract: A system for, and method of, assigning code blocks to constituent decoding units in a turbo decoding system having parallel decoding units. In one embodiment, the system includes: (1) a resource model generator configured to generate a model that represents the constituent decoding units and memories thereof along two dimensions, (2) a decoding unit number calculator associated with the resource model generator and configured to determine, for each of the code blocks, a number of the constituent decoding units to use to decode subblocks of each of the code blocks, (3) a rectangle mapper associated with the decoding unit number calculator and configured to generate a mapping in which the code blocks are mapped to the model and (4) a code block assigner associated with the rectangle mapper and configured to assign the subblocks of each code block to the constituent decoding units in accordance with the mapping.

Abstract: An apparatus having a cache configured as N-way associative and a controller circuit is disclosed. The controller circuit may be configured to (i) detect one of a cache hit and a cache miss in response to each of a plurality of access requests to the cache, (ii) detect a collision among the access requests, (iii) queue at least two first requests of the access requests that establish a speculative collision, the speculative collision occurring where the first requests access a given congruence class in the cache and (iv) delay a line allocation to the cache caused by a cache miss of a given one of the first requests while the given congruence class has at least N outstanding line fills in progress.

Abstract: A communication system (e.g., a hard drive) having a random-access memory (RAM) for storing trapping-set (TS) information that the communication system generates on-line during a special operating mode, in which low-density parity-check (LDPC)-encoded test codewords are written to a storage medium and then read and decoded to discover trapping sets that appear in candidate codewords produced by an LDPC decoder during decoding iterations. The discovered trapping sets are filtered to select a subset of trapping sets that satisfy specified criteria. The discovery and filtering of trapping sets is performed based on error vectors that are calculated using the a priori knowledge of original test codewords. The TS information corresponding to the selected subset is stored in the RAM and accessed as may be necessary to break the trapping sets that appear in candidate codewords produced by the LDPC decoder during normal operation of the communication system.

Abstract: A first virtual device is created including every logically addressable unit of a data storage server that utilizes data protection. A second virtual device is created including no logically addressable unit of the data storage server that utilizes data protection. Data transfers are disabled within all command phases of the first virtual device.

Abstract: In one embodiment, an LDPC decoder performs a targeted bit adjustment method to recover a valid codeword after the decoder has failed. In a first stage, a post processor initializes the decoder by saturating LLR values output by the decoder during the last (i.e., failed) iteration to a relatively small value. Then, two-bit trials are performed, wherein LLR values corresponding to two bits of the codeword are adjusted in each trial. Decoding is performed with the adjusted values, and if the number of unsatisfied check nodes exceeds a specified threshold, then a second stage is performed. The post processor initializes the decoder by saturating the LLR values output by the decoder during the last (i.e., failed) iteration of the first stage to a relatively small value. The second stage then performs single-bit adjustment trials, wherein one LLR value corresponding to one bit of the codeword is adjusted in each trial.

Abstract: A method, apparatus, and system of improved handling of clustered media errors in raid environment are disclosed. In one embodiment, a method includes starting a command timer when a firmware accepts a command from a host, tracking an amount of time the command spends on handling of a clustered media error through the command timer, and stopping the command timer when at least one of the command is completed and a time limit expires. The method may complete a read as a success when a host IO is a read command. The method may complete a write as a success, after writing parity, and data when the host IO may be a write command.

Abstract: Disclosed is a low dropout regulator that uses a load current tracking zero circuit to stabilize a feedback loop to prevent oscillations. The load current tracking zero circuit senses the DC component of the current flowing through the pass transistor of the low dropout regulator and uses the pass transistor current signal to control a multiplicative factor. The multiplicative factor multiplies the AC variations in the output voltage to generate the zero current.

Abstract: In a hard-disc drive, a defect region on the hard disc is detected by generating two statistical measures (e.g., ?1(k) and ?2(k)) based on signal values (e.g., x[n] or y[n]) and soft-decision values (e.g., L[n]) corresponding to the signal values. The measures are compared to detect the location of the defect region of the hard drive. Using the soft-decision values reduces fluctuations in a ratio of the statistical measures compared to a ratio formed from statistical measures that are not based on soft-decision values, resulting in a more-reliable test for detecting defect regions.

Abstract: A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

Abstract: A memory controller, a method of testing memory power management modes in an integrated circuit and an integrated circuit. In one embodiment, the memory controller includes a power management mode test controller couplable to a test access port and at least one memory core and configured to respond to a signal provided via the test access port by providing an ordered signal-setting sequence to the at least one memory core to cause the at least one memory core to enter into and exit from at least one memory power management mode.

Abstract: A method for reducing noise in an output of a voltage regulator at frequencies above a closed loop bandwidth, by providing a noise injection path for injecting external noise into the voltage regulator, where the noise injection path becomes active at the frequencies above the closed loop bandwidth, where the noise injection path reduces the noise in the output of the voltage regulator.

Abstract: A method for creating a design for an integrated circuit, by developing a set of delay cells where each of the cells in the set has a different delay time from the other cells in the set, and where each of the cells in the set has the same surface area, has the same pin-outs, has the same drive strength, and has the same input capacitance, where an originally-used cell in the set can be swapped out for a different replacement cell in the set without any impact on the design of the integrated circuit besides a change in delay time from the originally-used cell to the replacement cell.

Abstract: A lighted architectural mesh includes a plurality of interconnected wires forming a plurality of transverse openings. At least one light carrier is slidably received within at least one of said transverse openings. The at least one light carrier includes light nodes emitting light through the interstices on the front and/or rear side of the architectural mesh. The at least one light carrier further comprises a plurality of connecting elements, wherein the light emitter nodes of the at least one light element are releasably interconnected in series by the connecting elements.

Abstract: In one embodiment, a turbo equalizer is selectively operable in either first or second modes. In the first mode, layered (low-density parity-check (LDPC)) decoding is performed on soft-output values generated by a channel detector, where, for each full local decoder iteration, the updates of one or more layers of the corresponding H-matrix are skipped. If decoding fails to converge on a valid LDPC-encoded codeword and a specified condition is met, then LDPC decoding is performed in a second mode, where the updates of all of the layers of the H-matrix are performed for each full local decoder iteration, including the one or more layers that were previously skipped in the first mode. Skipping one or more layers in the first mode increases throughput of the decoder, while updating all layers in the second mode increases error correction capabilities of the decoder.

Abstract: A RAID system is provided in which the RAID controller of the system causes a predetermined number, N, of IO commands to be queued in a memory element, where N is a positive integer. After the N IO commands have been queued, the RAID controller writes N locks associated with the N IO commands in parallel to a service memory device. The RAID controller then writes N stripes of data and parity bits associated with the N IO commands to the PDs of the system to perform striping and parity distribution. If a catastrophic event, such as a power failure, occurs, the RAID controller reads the locks from the service memory device and causes parity to be reconstructed for the stripes associated with the locks. These features improve write performance while preventing the occurrence of data corruption caused by write holes.

Abstract: A planar galvanic cell arrangement for portable electronic device is provided. In one embodiment, a galvanic cell arrangement may include a flexible substrate including a surface area that forms a plane. The galvanic cell arrangement also includes a plurality of galvanic cells coupled with the flexible substrate within the surface area that forms the plane, and electrically connected with one another in series, each of the plurality of galvanic cells including a negative electrode and a positive electrode. Furthermore, the galvanic cell arrangement includes a first terminal coupled with the negative electrode at one end of the series, and second terminal coupled with the positive electrode at an opposite end of the series. The plurality of galvanic cells being configured to provide electrical power to the portable electronic device via the first and second terminal, based on the plurality of galvanic cells being exposed to an aqueous electrolyte.