Abstract: A switched preconditioner circuit is provided at the power input end of a light source to effectively drop the voltage of the light source to zero volts whenever the light source is required to be in an OFF state thereby eliminating the problem of unwanted current through the light source. The preconditioner circuit may include a terminal connected to a first power potential, a terminal connected to a power node at the power input end of the light source, and an input to receive a preconditioner control signal to place the preconditioner circuit in one of an ON state and an OFF state. The preconditioner circuit supplies the voltage to the power node in its ON state and effectively eliminates the voltage to the power node in its OFF state.

Abstract: Data latch circuit and method of low power decision feedback equalization (DFE) system is disclosed. In one embodiment, the data latch circuit of the of a decision feedback equalization (DFE) system includes a first parallel n-channel metal-oxide-semiconductor field-effect transistor (NMOS) pair to input a differential input voltage. The data latch circuit also includes a second parallel NMOS pair coupled to the first parallel NMOS pair to input a decision feedback equalization (DFE) voltage. The data latch circuit further includes a cross-coupled PMOS pair to generate a positive feedback to the first parallel NMOS pair and/or the second parallel NMOS pair. In addition, the data latch circuit includes a cross-coupled NMOS pair to escalate the positive feedback. Furthermore the data latch circuit includes a latching circuit to generate a signal data based on the sinking of a current at an input of the latching circuit and/or the positive feedback.

Abstract: Methods and associated structures for utilizing write-back cache management modes for local cache memory of disk drives coupled to a storage controller while maintaining data integrity of the data transferred to the local cache memories of affected disk drives. In one aspect hereof, a state machine model of managing cache blocks in a storage controller cache memory maintains blocks in the storage controller's cache memory in a new state until verification is sensed that the blocks have been successfully stored on the persistent storage media of the affected disk drives. Responsive to failure or other reset of the disk drive, the written cache blocks may be re-written from the copy maintained in the cache memory of the storage controller. In another aspect, an alternate controller's cache memory may also be used to mirror the cache blocks from the primary storage controller's cache memory as additional data integrity assurance.

Abstract: Methods and structures for assuring proper sequencing of processing of SAS frames received over multiple physical ports of a SAS wide port. A frame scheduler element is communicatively coupled with a SAS transport layer and with a corresponding plurality of link layers operable as a SAS wide port. The frame scheduler receives a request from the transport layer to locate or select a next received frame for further processing. The frame scheduler interacts with the plurality of link layer processing elements having received frames stored within to locate the link layer that has the requested next frame. The frame scheduler then coordinates operation of that link layer and the transport layer to effectuate the transfer of the required next frame.

Abstract: A data volume rebuilder reduces the time required to reconstruct lost data in a RAID protected data volume operating with a failed physical disk drive. A data volume rebuilder uses the remaining functioning physical disk drives in the RAID protected data volume operating with the failed disk to regenerate the lost data and populate a virtual hot spare store allocated in a separate RAID protected data volume. The recovered data is distributed across the physical disk drives supporting the virtual hot spare store. Once the virtual hot spare store is populated, the data volume can recover from a subsequent failure of a second physical disk drive in either RAID group. After replacement of the failed physical disk drive, the data volume rebuilder moves the recovered data from the virtual hot spare store to the new physical disk drive.

Abstract: An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.

Abstract: An electrically programmable fuse controller, a method of controlling a drive voltage of an integrated circuit (IC) and an IC incorporating the controller or the method. In one embodiment, the controller includes a VID eFuse controller configured to receive and write a voltage identifier to an associated eFuse and thereafter allow the voltage identifier to be read from the eFuse and employed to set a drive voltage of an integrated circuit associated with the VID eFuse controller.

Abstract: Systems and methods herein provide for protecting data using snapshots and images of those snapshots to quickly recreate data upon request. For example, a storage controller of a data storage system allocates a period of time between creating snapshots of data in a first storage volume of the data storage system. The controller then logs received write requests to the first storage volume and generates snapshot of data in the first storage volume based on the allocated period of time. Thereafter, the controller may receive a request to recreate data. The controller locates the snapshot in the first storage volume based on that request to recreate the data. In doing so, the controller generates a snapshot image in a second storage volume. The controller then retrieves logged write requests and applies them to the snapshot image to recreate the data in the second storage volume.

Abstract: A method for dynamic storage tiering may comprise: detecting a storage hot-spot located in a first storage pool; and creating a first point-in-time copy of a virtual volume including the storage hot-spot located in the first storage pool in a second storage pool according to the detecting. A system for dynamic storage tiering may comprise: means for detecting a storage hot-spot located in a first storage pool; and means for creating a first point-in-time copy of a virtual volume including the storage hot-spot located in the first storage pool in a second storage pool according to the detecting.

Abstract: A physical layer device for interfacing with multiple computing devices includes a digital core and first and second analog front ends. The digital core is operative to perform one or more functions of the physical layer device. Each of the first and second analog front ends is operative to perform signal conversion between a digital domain and an analog domain. The physical layer device further includes a digital switching circuit coupled to the digital core and to the first and second analog front ends. The digital switching circuit is operative to electrically connect the digital core to the first analog front end or the second analog front end as a function of a control signal applied to the digital switching circuit.

Abstract: The present invention provides methods and apparatus for accomplishing a optical direct write phase shift lithography. A lithography system and method are provided wherein a mirror array is configured to generate vortex phase shift optical patterns that are directed onto a photosensitive layer of a substrate. The lithography methods and systems facilitate pattern transfer using such vortex phase shift exposure patterns.

Abstract: In an N+1 protection scheme for a router in a data or telecommunications network, a processor-based protection unit has a replica device handle, corresponding to each of the N working units, stored in the protection unit's local memory. Each replica device handle is an image of the connections provided by the corresponding working unit. In one implementation, upon detection of a failure of one of the working units, the router's controller unit sends a single command to instruct the protection unit to reconfigure itself using the corresponding locally stored replica device handle to assume the routing functions of the failed working unit.

Abstract: A luminaire for lighting a traffic surface in a tunnel is disclosed, wherein the luminaire has light sources disposed in an array for casting light on a traffic surface and structure for controlling and directing the light, such as a reflector or refractor lens. The luminaires are positioned along the length of the tunnel at angles to the traffic surface facilitating optimal use of the generated light. The luminaire is configured as a module that can be quickly installed into a support track mounted on the tunnel walls, and is dust and waterproof to endure mechanical and high pressure water cleaning by conventional tunnel washers. The luminaire is particularly well suited to employ light emitting diodes for generating and casting light.

Abstract: Apparatuses and methods for increasing well distributed, high quality-factor on-chip capacitance of integrated circuit devices are disclosed. In one aspect, an integrated circuit device structure includes a first metal line implemented on a metallization layer of a semiconductor substrate, the first metal line having a first set of metal fingers extending therefrom; and a second metal line electrically isolated from the first metal line, the second metal line having a second set of metal fingers extending therefrom, the first set of metal fingers and the second set of metal fingers capacitively coupled. The basic structure of metal lines with interlocking metal fingers may be repeated on multiple adjacent metallization layers, with the metal lines oriented either in parallel or perpendicular.

Abstract: A method of generating an IRF pattern for testing an IC and a test pattern generator are disclosed. In one embodiment, the method includes: (1) identifying a path of the integrated circuit for inline resistive fault pattern generation, (2) determining if the path is a minimal slack path of the IC and (3) generating, when the path is the minimal slack path, a restricted inline resistive fault pattern for the path using only a capture polarity having a minimal inherent margin.

Abstract: Various embodiments of the present invention provide systems and methods for determining fly-height adjustments. For example, various embodiments of the present invention provide storage devices that include a storage medium, a read/write head assembly disposed in relation to the storage medium (278), and a SAM based fly-height adjustment circuit (214). The storage medium (278) includes a plurality of servo data regions (110) that each include a servo address mark (154). The SAM based fly-height adjustment circuit (214) receives the servo address mark (154) from the plurality of servo data regions (110) via the read/write head assembly (276), and calculates a first harmonics ratio (445) based on the received data. The first harmonics ratio (445) is compared with a second harmonics ratio (450) to determine an error (365) in the distance (295) between the read/write head assembly (276) and the storage medium (278).

Abstract: The present disclosure is directed to a method for communication between an initiator system and a block storage cluster. The method may comprise receiving an initial data request from the initiator system to a first storage system, a portion of the data requested in the initial data request is not stored by the first storage system, but is stored by a second storage system; retrieving the portion of the data that is stored by the second storage system; forwarding the portion of the data to the initiator system; and transmitting a referral list comprising at least one referral from the first storage system to the initiator system, wherein the initiator system is configured for maintaining a referral cache based on the referral list, and a subsequent data request initiated by the initiator system is directed to the block storage cluster based on the referral cache.

Abstract: In described embodiments, a thin film transistor (TFT) liquid crystal display (LCD) structure incorporates a white light emitting diode (LED) structure for backlighting. White LEDs are formed behind each TFT cell, allowing for display “black” as a function of a nematic layer, on the TFT substrate, while increasing intensity of the LED LCD backlight structure. A lens structure might be formed between the LEDs and the TFT substrate to reduce a number of LED sources for a given backlight intensity.

Abstract: Data-processing systems and methods are disclosed, including an I/O interface for managing the transfer of data between a processor and at least one memory. A processor can be associated with the I/O interface, such that the processor generically assembles a first or prior frame from among a plurality of frames, transmits the first or prior frame from among the plurality of frames over the I/O interface and thereafter processes and assembles a subsequent or second frame from among the plurality of frames while the first frame is transmitting, thereby providing enhanced flexibility and speed for the assembly and transmission of the plurality of frames across the I/O interface. The methods and systems disclosed also permit processor (i.e., software control) flexibility in managing the overall order and priority of frame transmission and protocol management, while enhancing hardware performance with respect to the sending of frames and control sequences without requiring real time interaction from the processor.

Abstract: In one embodiment, an adaptive clock recovery (ACR) system generates a current delay-offset estimate value (DOE(i)) using a window technique that selects the larger of (i) the maximum delay-offset value (DOP) in the previous window and (ii) the maximum delay-offset value so far (DOM) in current window. This windowing technique can be implemented without having to store all of the individual values over a specified window size, as in a conventional sliding window technique. This windowing technique can be used to find extreme (i.e., either maximum or minimum) values for applications other than ACR systems.