Abstract: A lighted architectural mesh includes a plurality of interconnected wires forming a plurality of transverse openings. At least one light carrier is slidably received within at least one of said transverse openings. The at least one light carrier includes light nodes emitting light through the interstices on the front and/or rear side of the architectural mesh. The at least one light carrier further comprises a plurality of connecting elements, wherein the light emitter nodes of the at least one light element are releasably interconnected in series by the connecting elements.

Abstract: Described embodiments provide coherent processing of hash operations of a network processor having a plurality of processing modules. A hash processor of the network processor receives hash operation requests from the plurality of processing modules. A hash table identifier and bucket index corresponding to the received hash operation request are determined. An active index list is maintained for active hash operations for each hash table identifier and bucket index. If the hash table identifier and bucket index of the received hash operation request are in the active index list, the received hash operation request is deferred until the hash table identifier and bucket index corresponding to the received hash operation request clear from the active index list. Otherwise, the active index list is updated with the hash table identifier and bucket index of the received hash operation request and the received hash operation request is processed.

Abstract: Described embodiments provide a packet classifier of a network processor having a plurality of processing modules. A scheduler generates a thread of contexts for each tasks generated by the network processor corresponding to each received packet. The thread corresponds to an order of instructions applied to the corresponding packet. A multi-thread instruction engine processes the threads of instructions. A function bus interface inspects instructions received from the multi-thread instruction engine for one or more exception conditions. If the function bus interface detects an exception, the function bus interface reports the exception to the scheduler and the multi-thread instruction engine. The scheduler reschedules the thread corresponding to the instruction having the exception for processing in the multi-thread instruction engine. Otherwise, the function bus interface provides the instruction to a corresponding destination processing module of the network processor.

Abstract: The present disclosure is directed to a system and a method for optimizing redundancy restoration in distributed data layout environments. The system may include a plurality of storage devices configured for providing data storage. The system may include a prioritization module communicatively coupled to the plurality of storage devices. The prioritization module may be configured for determining a restoration order of at least a first data portion and a second data portion when a critical data failure occurs. The system may include a restoration module communicatively coupled to the plurality of storage devices and the prioritization module, the restoration module configured for restoring at least the first data portion and the second data portion based upon the restoration order.

Abstract: A method for communication between an initiator system and a storage cluster. The method comprises receiving an initial I/O request from the initiator system to a first storage system; providing a referral response from the first storage system to the initiator system, the referral response providing information for directing the initiator system to a second storage system; notifying the second storage system regarding the referral response via a prefetch notice, the prefetch notice including an operation type and address information for accessing requested data; when the initial I/O request is a read request, prefetching at least a portion of the requested data stored in the second storage system in to a cache; receiving a second I/O request from the initiator system to the second storage system; and providing to the initiator system the portion of the prefetched data from the cache of the second storage system.

Abstract: Described embodiments provide a hash processor for a system having multiple processing modules and a shared memory. The hash processor includes a descriptor table with N entries, each entry corresponding to a hash table of the hash processor. A direct mapped table in the shared memory includes at least one memory block including N hash buckets. The direct mapped table includes a predetermined number of hash buckets for each hash table. Each hash bucket includes one or more hash key and value pairs, and a link value. Memory blocks in the shared memory include dynamic hash buckets available for allocation to a hash table. A dynamic hash bucket is allocated to a hash table when the hash buckets in the direct mapped table are filled beyond a threshold. The link value in the hash bucket is set to the address of the dynamic hash bucket allocated to the hash table.

Abstract: A method for detecting a media type of an optical disc system comprising the steps of (A) checking for a first wobble signal associated with a first media type, (B) if step (A) detects the first wobble signal, operating the optical disc system as the first media type, (C) checking for a second wobble signal associated with a second media type, and (D) if step (C) detects the second wobble signal, operating the optical disc system as the second media type.

Abstract: An instrument is provided for cutting tissue having a housing, a shaft extending from the housing to a distal end with an opening, and a guide tube extending from the distal end through the opening for receiving a guide wire through the shaft and housing. A movable blade shuttle having a blade is provided at the distal end. The blade shuttle's travel is guided by the guide tube when the blade shuttle and blade is extended from the distal end opening to cut tissue and retracted back through the distal end opening. The housing has a pivotal actuator member mechanically coupled to the blade shuttle to remotely control movement of the blade shuttle at the instrument's distal end. The instrument may be used for longitudinal cutting of tissue at remote sites in the body of a patient to provide incisions of precise depth and length over a controlled path of a guide wire.

Abstract: Efficient power management method in integrated circuit through a nanotube structure is disclosed. In one embodiment, a method includes patterning a nanotube structure adjacent to a transistor layer of an integrated circuit. The transistor layer may be above a semiconductor substrate. The transistor layer above the semiconductor substrate may comprise a plurality of transistors. The method also includes supplying power to the plurality of transistors through one or more power sources. In addition, the method includes coupling the plurality of transistors in the transistor layer to the one or more power sources based on a state of the nanotube structure.

Abstract: A system and method for customizing a SCSI error response received from a SCSI target in a storage network environment is disclosed. In a method for customizing a SCSI error response received from a SCSI target in a storage network environment, a SCSI command is received from a SCSI initiator by a SCSI to ATA bridge. The received SCSI command is translated to provide an ATA command. The ATA command is then sent to an ATA drive. The ATA command is executed by the ATA drive. During execution, if an error occurs, an ATA error response is sent by the ATA drive to the SCSI to ATA bridge. The received ATA error response is translated to a SCSI error response. The SCSI to ATA bridge then obtains a customized SCSI error response using an error look-up table. Further the customized SCSI error response is sent to the SCSI initiator.

Abstract: The present invention is a method for providing atomicity for host write Input/Outputs (I/Os) in a Continuous Data Protection (CDP)-enabled volume. When a host overwrite Input/Output (I/O) is initiated by a host against a data block of the CDP-enabled volume, the method may include creating an in-flight write log entry and providing the in-flight write log entry to an in-flight write log of the CDP-enabled volume. The in-flight write log entry may correspond to the host overwrite I/O. The method may further include locating mapping table information in a mapping table of the CDP-enabled volume. The mapping table information may correspond to the data block. The method may further include recording a journal entry in a journal of the CDP-enabled volume. The journal entry may include a journal entry timestamp which corresponds to the host overwrite I/O. The method may further include allocating a storage location for the host overwrite I/O.

Abstract: A device may include protective housing including a battery backup unit circuit, at least one L-hook disposed on the protective housing including a battery backup unit circuit, the L-hook configured for being coupled to a test point loop disposed on a memory module, and/or at least one retention arm configured to couple the protective housing including a battery backup unit circuit to the memory module. Additionally, a RAID controller card and a method utilizing the device are disclosed.

Abstract: A technique for enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.

Abstract: The present invention is a method for providing address decode and Virtual Function (VF) migration support in a Peripheral Component Interconnect Express (PCIE) multi-root Input/Output Virtualization (IOV) environment. The method may include receiving a Transaction Layer Packet (TLP) from the PCIE multi-root IOV environment. The method may further include comparing a destination address of the TLP with a plurality of base address values stored in a Content Addressable Memory (CAM), each base address value being associated with a Virtual Function (VF), each VF being associated with a Physical Function (PF). The method may further include when a base address value included in the plurality of base address values matches the destination address of the TLP, providing the matching base address value to the PCIE multi-root IOV environment by outputting from the CAM the matching base address value.

Abstract: The present invention is directed to a method and system of intelligent dummy filling placement to reduce inter-layer capacitance caused by overlaps of dummy filling area on successive layers. The method and system treats each consecutive pair of layers together so as to minimize dummy filling overlaps between each layer. In particular, dummy fill features on each layer may be placed in a checkerboard pattern to avoid overlaps. As such, the present invention may eliminate large overlap area of the dummy patterns on consecutive layers by utilizing intelligent dummy filling placement.

Abstract: A method of fabricating an interconnection between a region of copper material and a conducting region is disclosed. The method includes a step of forming a region of tin material and a step of forming a region of nickel material. The method also includes a step of melting the tin material to induce formation of a nickel/tin/copper intermetallic composition at an interface between the region of copper material and the conducting region. The region of tin material and the region of nickel material define the interface between the region of copper material and the conducting region.

Abstract: The present invention is a method for handling disk drives in a Redundant Array of Inexpensive Disks (RAID) configuration. The method may include detecting a disk drive received via insertion of the disk drive in a disk drive slot of an enclosure of the RAID configuration. Prior to the disk drive being received, it may be that fewer than a maximum number of supported disk drives are configured. It may also be the case that, after the disk drive is received, no more than the maximum number of supported drives are in-place within the enclosure of the RAID configuration. In such instances, and when the insertion is a cold insertion into an empty disk drive slot, the method may further include marking the disk drive as Un-configured good alias Ready. Further, if the disk drive is inserted into a missing disk drive slot and has a smaller storage capacity than that of the replaced disk drive previously in place within the missing disk drive slot, the method may further include marking the disk drive as FAIL.

Abstract: Methods and systems for rapid creation of copies of a mapped storage volume. A new copy of a mapped storage volume is created by copying the mapping table and updating meta-data associated with the new copy and any ancestral parents thereof. The physical blocks remain untouched when creating a new copy as does any meta-data associated with the physical blocks. Rather, reference meta-data associated with each physical block is updated only in response to processing of a write request to an identified block of an identified copy of the mapped storage volume. Thus copy creation is rapid as compared to prior techniques reliant on reference counters.

Abstract: Various embodiments of the present invention provide systems and methods for using channel bit density estimates to adjust fly-height. For example, various embodiments of the present invention provide methods for adaptively adjusting fly-height. Such methods include providing a storage medium that includes information corresponding to a process data set, and a read/write head assembly that is disposed a variable distance from the storage medium. The process data set is accessed from the storage medium. A first channel bit density estimate is adaptively calculated based at least in part on the process data set and a second channel bit density estimate that was previously calculated. The variable distance is modified based at least in part on the first channel bit density estimate. A third channel bit density is adaptively calculated based at least in part on the process data set and a fourth channel bit density estimate that was previously calculated.

Abstract: A method for reducing the size of a DFA associated with a regular expression separates the functions of locating subexpressions within the DFA and determining if the located subexpressions satisfy a regular expression. For example, the functions of (1) locating subexpressions in a range asserting expression and, (2) determining whether the subexpressions satisfy the range of the range asserting expression are partitioned. In one embodiment, a first component may locate the subexpressions in a data stream using one or more DFAs, while a second component determines if the located subexpressions satisfy the range. In this embodiment, because the DFAs are not configured to determine a relationship between subexpressions, such as a range between subexpressions, the size of the resultant DFA may be significantly reduced.