Abstract: The present invention is directed to a method for providing Quality Of Service (QoS)-based storage tiering and migration in a storage system. The method allows for configurable application data latency thresholds to be set on a per user basis and/or a per application basis so that a storage tiering mechanism and/or a storage migrating mechanism may be triggered for moving application data to a different class of storage.

Abstract: A method of manufacturing an electronic device package. Coating a first side of a metallic layer with a first insulating layer and coating a second opposite side of the metallic layer with a second insulating layer. Patterning the first insulating layer to expose bonding locations on the first side of the metallic layer, and patterning the second insulating layer such that remaining portions of the second insulating layer on the second opposite side are located directly opposite to the bonding locations on the first side. Selectively removing portions of the metallic layer that are not covered by the remaining portions of the second insulating layer on the second opposite side to form separated coplanar metallic layers. The separated coplanar metallic layers include the bonding locations. Selectively removing remaining portions of the second insulating layer thereby exposing second bonding locations on the second opposite sides of the separated coplanar metallic layers.

Abstract: The present invention is directed to a system and method for emulating a serial small computer system interface (SAS) connection for direct attached serial advanced technology attachment (SATA) communication are disclosed. A system in accordance with the present invention includes a host controller. The host controller includes a physical interface for accepting at least one of a SAS connection or a direct attached SATA device. A common interface logic configured to receive SAS communications and SATA communications having a SAS emulated connection is included in the host controller. An emulation logic is communicatively coupled to the common interface logic. The emulation logic being configured to determine a value of a ConnectedSata signal based on the state of a SATA link state machine.

Abstract: In described embodiments, a method of generating an identifier for a disk includes the steps of requesting an ASCII identification string for the disk and generating a padded string by processing the ASCII identification string into a predetermined number of bytes. The padded string is divided into portions and an encoded value is generated for each portion. The two or more encoded values for the portions are combined into a candidate value compatible with a World-Wide Name (“WWN”). The candidate value is compared to a list of previously generated candidate values and if the candidate value differs from the values in the list, the candidate value is included in the list of generated values and the candidate value is provided as the system-wide name for the disk.

Abstract: A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.

Abstract: Apparatus and methods for full address resolution in a zoning SAS expander. A single memory circuit is used in a zoning SAS expander to store zone information associated with the SAS address (e.g., WWN) of devices exchanging information through the expander. The source and destination addresses in a received SAS frame are used as inputs to the memory circuit to generate outputs of the memory circuit representing the source and destination zone group identifiers. These outputs are then applied to the zone permission table to determine the zoning permission for forwarding the frame through the expander. Pipelined logic within the expander sequences the operations of the memory circuit and the zone permissions table to account for clock cycle delays in processing of each. In one exemplary embodiment, the memory circuit is a content addressable memory (CAM). In another exemplary embodiment, the CAM also includes port routing information.

Abstract: Various embodiments of the present invention provide systems and methods for validating elements of storage devices. A an example, various embodiments of the present invention provide semiconductor devices that include a write path circuit, a read path circuit and a validation circuit. The write path circuit is operable to receive a data input and to convert the data input into write data suitable for storage to a storage medium. The read path circuit is operable to receive read data and to convert the read data into a data output. The validation circuit is operable to: receive the write data, augment the write data with a first noise sequence to yield a first augmented data series; and augment a derivative of the first augmented data series with a second noise sequence to yield the read data.

Abstract: Disclosed is a store and forward device that reduces latency. The store and forward device allows front end devices having various transfer protocols to be connected in a single path through a RAM, while reducing latency. Front end devices that transfer data on a piecemeal basis are required to transfer all of the data to a RAM prior to downloading data to a back end. Front end devices that transfer data in a single download begin the transfer of data out of a RAM as soon as a threshold value is reached. Hence, the latency associated with downloading all of the data into a RAM 118 and then transferring all of the data out of the RAM is eliminated.

Abstract: A method for conserving power in a device. The method generally includes the steps of (A) generating a polarity signal by analyzing a current one of a plurality of data items having a plurality of data bits, the polarity signal having an inversion bit indicating that the current data item is to be stored in one of (i) an inverted condition and (ii) a non-inverted condition relative to a normal condition such that a majority of the data bits have a first logic state, wherein reading one of the data bits having the first logic state consumes less power than reading one of the data bits having a second logic state, (B) selectively either (i) inverting the current data item or (ii) not inverting current the data item based on the inversion bit and (C) storing the current data item in a plurality of single-ended bit cells in the device.

Abstract: A processor (e.g., a Digital Signal Processor (DSP) core) rewinds a pipeline of instructions upon a watchpoint event in an instruction being processed. The program execution ceases at the instruction in which the watchpoint event occurred, while the instruction and subsequent instructions are cancelled, keeping the hardware components associated with executing the program in their previous states, prior to the watchpoint. The rewind is such that the program is refetched to enable execution to continue from the instruction in which the watchpoint event occurred. The watchpoint event is executed in a “break before make” manner.

Abstract: A modular and redundant storage controller system includes management modules, controller modules and an interconnect module. The management modules provide direct-current power and signals to respective controller modules. The controller modules include respective signal interfaces, direct-current interfaces, and interconnect interfaces. The signal interfaces couple the controllers to a respective management module. The direct-current interfaces couple the controllers to a respective management module. The interconnect module includes a pair of connectors arranged to couple a pair of the controller modules via the respective interconnect module interfaces.

Abstract: The present invention is directed to a method for providing data element placement in a storage system via a Dynamic Storage Tiering (DST) mechanism, such that improved system efficiency is promoted. For example, the DST mechanism may implement an algorithm for providing data element placement. The data elements (ex.—virtual volume hot-spots) may be placed into storage pools, such that usage of higher performing storage pools is maximized. Hot-spots may be detected by dynamically measuring load on LBA ranges. Performance of the storage pools may be measured on an ongoing basis. Further, the hot-spots may be ranked according to load, while storage pools may be ranked according to measured performance. If a hot-spot's load decreases, the hot-spot may be moved to a lower performing storage pool. If a hot-spot's load increases, the hot-spot may be moved to a higher performing storage pool.

Abstract: An embodiment of the present invention is disclosed to include a fiber channel target device for receiving information in the form of frames and including a controller device coupled to a microprocessor for processing the frames received from the host, at least one receive buffer for storing the frames and having a buffer size, the controller device issuing credit to the host for receipt of further frames in a manner wherein only one microprocessor is needed to process the frames while maintaining a buffer size that is as small as the number of first type of frames that can be received by the fiber channel target device from the host.

Abstract: An apparatus including a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit may be configured to generate a demodulated signal in response to a modulated signal and a seed value selected in response to a first control signal. The second circuit may be configured to generate a second control signal in response to the demodulated signal. The third circuit may be configured to generate the first control signal in response to the second control signal, a compensation signal, and the first control signal, where generation of the first control signal includes adding the second control signal, the compensation signal, and a latched version of the first control signal. Generation of the latched version of the first control signal may include sampling the first control signal in response to a clock signal. The compensation signal may compensate for variation in the clock signal.

Abstract: An electronic device includes a heat dissipating component located over a substrate. An isolation trench is formed in the substrate adjacent the component. A contact region of the substrate is bounded by the trench. An electrically isolated contact is located over and in contact with the contact region. The electrically isolated contact and the contact region provide a thermally conductive path to the substrate.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a video signal and macroblock data in response to decoding one or more bins on a binary signal. The second circuit may be configured to, in parallel (i) generate the binary signal in response to a bitstream signal and an initial context information and (ii) calculate subsequent context information.

Abstract: A system and method for sharing peripheral first-in-first-out (FIFO) resources is disclosed. In one embodiment, a system for utilizing peripheral FIFO resources includes a processor, a first peripheral FIFO controller and a second peripheral FIFO controller coupled to the processor for controlling buffering of first data and second data associated with the processor respectively. Further, the system includes a merge module coupled to the first peripheral FIFO controller and the second peripheral FIFO controller for merging a first FIFO channel associated with the first peripheral FIFO controller and a second FIFO channel associated with the second peripheral FIFO controller based on an operational state of the first FIFO channel and an operational state of the second FIFO channel respectively. Also, the system includes a first FIFO and a second FIFO coupled to the merge module via the first FIFO channel and the second FIFO channel respectively.

Abstract: An apparatus and method for determining the power consumption of one or more disk arrays are described. Power consumption information for various hardware components of the array, especially that for the disk drives since these consume more than 90% of the required power, are stored in a static data table in a database which may be controller firmware. Through inspection of this table and the chosen state of the individual disk drives as directed by a controller, one may determine the power use of the array.

Abstract: A method for contour reduction in a digital picture is disclosed. The method generally includes the steps of (A) buffering a plurality of luma samples in a current line of the digital picture, each of the luma samples having a respective input value, (B) calculating a plurality of horizontal sum-of-signs along the current line, wherein each of the horizontal sum-of-signs comprises a sum of a plurality of amplitude differences between pairs the luma samples from the current line and (C) generating a plurality of output value based on the horizontal sum-of-signs, one of the output values for each one of the luma samples.

Abstract: An LDPC decoder that implements an iterative message-passing algorithm, where the improvement includes a pipeline architecture such that the decoder accumulates results for row operations during column operations, such that additional time and memory are not required to store results from the row operations beyond that required for the column operations.