Patents Assigned to LSI
  • Method and apparatus for determining a second picture for temporal direct-mode block prediction
    Patent number: 8036271
    Abstract: A method for determining a first and a second reference picture used for inter-prediction of a macroblock, comprising the steps of (A) finding a co-located picture and block, (B) determining a reference index, (C) mapping the reference index to a lowest valued reference index in a current reference list and (D) using the reference index to determine the second reference picture.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: October 11, 2011
    Assignee: LSI Corporation
    Inventors: Lowell L. Winger, Simon Booth, Elliot N. Linzer, Ho-Ming Leung
  • METHOD FOR IMPLEMENTING MULTI-ARRAY CONSISTENCY GROUPS USING A WRITE QUEUING MECHANISM
    Publication number: 20110246423
    Abstract: A method for implementing multi-array consistency groups includes applying a write Input/Output (I/O) queue interval to a Logical Unit (LU) member of a consistency group (CG). The method also includes marking each write I/O with a timestamp and suspending I/O from the participating storage array to the LU member of the CG upon the participating storage array receiving a snapshot request from a master storage array. The method further includes determining whether the snapshot request timestamp is within the write I/O queue interval of the participating storage array.
    Type: Application
    Filed: January 23, 2009
    Publication date: October 6, 2011
    Applicant: LSI CORPORATION
    Inventor: Martin Jess
  • Frequency-based approach for detection and classification of hard-disc defect regions
    Patent number: 8031420
    Abstract: In a hard-disc drive read channel, frequency-based measures are generated at two different data frequencies (e.g., 2T and DC) by applying a transform, such as a discrete Fourier transform (DFT), to signal values, such as ADC or equalizer output values, corresponding to, e.g., a 2T data pattern stored on the hard disc. The frequency-based measures are used to detect defect regions on the hard disc and/or to classify defect regions as being due to either thermal asperity (TA) or drop-out media defect (MD).
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: October 4, 2011
    Assignee: LSI Corporation
    Inventors: George Mathew, Yang Han, Shaohua Yang, Zongwang Li, Yuan Xing Lee
  • Battery backup system with sleep mode
    Patent number: 8030897
    Abstract: The present invention concerns an apparatus comprising a charger circuit and a control circuit. The charger circuit may be configured to generate a first power down control signal and a second power down control signal in response to (i) a first charge signal, (ii) a second charge signal, (iii) a supply voltage, and (iv) a host control signal. The control circuit may be configured to generate the first charge signal and the second charge signal in response to a first battery signal and a second battery signal. The control circuit may enter a power down state in response to the host control signal initiating the power down state.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: October 4, 2011
    Assignee: LSI Corporation
    Inventors: Lakshmana M. Anupindi, Brad D. Marshall, R. Brian Skinner
  • Controller, program and methods for communicating with devices coupled to the controller
    Patent number: 8032665
    Abstract: A controller coupled to a redundant array of inexpensive disks (RAID) includes a processor and a non-volatile memory element. The processor has an input/output port that is configurable in one of an open-drain driver configuration, a high-impedance driver configuration and a totem-pole driver configuration. The totem-pole driver configuration is capable of supplying sufficient current to operate a slave device coupled to the input/output port. Firmware stored in the non-volatile memory device dynamically adjusts the driver configuration to prevent negative voltage swings in a signal communicated via the input/output port.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: October 4, 2011
    Assignee: LSI Corporation
    Inventors: Jayant Mohan Daftardar, Justin R. McCollum
  • Performance adaptive video encoding with concurrent decoding
    Patent number: 8031766
    Abstract: An encoder circuit, a task scheduler circuit and a decoder circuit. The encoder circuit may be configured to (i) generate one or more first status signals in response to one or more report signals and (ii) perform video encoding tasks based on available central processing unit (CPU) cycles and memory bandwidth. The task scheduler circuit may be configured to (i) generate a control signal and the one or more report signals in response to the one or more first status signals. The decoder circuit may be configured to (i) generate one or more second status signals and (ii) perform concurrent decoding while the encoder circuit performs adaptive video encoding tasks in response to the control signal.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: October 4, 2011
    Assignee: LSI Corporation
    Inventor: Guy Cote
  • AMPLITUDE-BASED APPROACH FOR DETECTION AND CLASSIFICATION OF HARD-DISC DEFECT REGIONS
    Publication number: 20110235490
    Abstract: In a hard-disc drive, a defect region on the hard disc is classified as corresponding to either thermal asperity (TA) or media defect (MD) by generating two statistical measures. A first measure (e.g., ?1) is based on (i) the magnitudes of one or both of signal values (e.g., equalizer input or output signal values) and the corresponding expected values of those signal values and (ii) the signs of one or both of the signal values and the expected signal values. A second measure (e.g., ?2) is based on the magnitudes of one or both of the signal values and the expected signal values, but not the signs of either the signal values or the expected signal values. The two measures are then compared to determine whether the defect region corresponds to TA or MD.
    Type: Application
    Filed: March 23, 2010
    Publication date: September 29, 2011
    Applicant: LSI Corporation
    Inventors: Shaohua Yang, George Mathew, Yang Han, Zongwang Li, Yuan Xing Lee
  • EFFICIENT MIRRORING OF DATA ACROSS STORAGE CONTROLLERS
    Publication number: 20110238938
    Abstract: A method includes multicasting an Input/Output (I/O) data associated with a host computing device through a multicast device associated with a storage controller coupled to another storage controller in a redundant configuration, and minoring, through the multicasting, the I/O data across the storage controller and the another storage controller through a bus utilized to couple the storage controller and the another storage controller. The method also includes transmitting an early write status message to the host computing device following the minoring of the I/O data across the storage controller and the another storage controller. The early write status message is associated with a successful completion of the mirroring of the I/O data across the storage controller and the another storage controller prior to the I/O data being written to a storage device associated therewith.
    Type: Application
    Filed: October 30, 2008
    Publication date: September 29, 2011
    Applicant: LSI Corporation
    Inventors: John R Kloeppner, Mohamad El-Batal
  • DETECTION OF HARD-DISC DEFECT REGIONS USING SOFT DECISIONS
    Publication number: 20110235204
    Abstract: In a hard-disc drive, a defect region on the hard disc is detected by generating two statistical measures (e.g., ?1(k) and ?2(k)) based on signal values (e.g., x[n] or y[n]) and soft-decision values (e.g., L[n]) corresponding to the signal values. The measures are compared to detect the location of the defect region of the hard drive. Using the soft-decision values reduces fluctuations in a ratio of the statistical measures compared to a ratio formed from statistical measures that are not based on soft-decision values, resulting in a more-reliable test for detecting defect regions.
    Type: Application
    Filed: March 25, 2010
    Publication date: September 29, 2011
    Applicant: LSI CORPORATION
    Inventors: Shaohua Yang, Weijun Tan
  • Staged Scenario Generation
    Publication number: 20110239171
    Abstract: A method of verifying integrated circuit designs, by constructing a series of atomic generators in a staged, hierarchical order, applying a lowest of the hierarchical generator stages to device level test cases of the verification process, applying a highest of the hierarchical generator stages to system level test cases of the verification process, reusing code written for and used in the lowest hierarchical generator stage in a next higher generator stage, creating a constraint scenario in the highest hierarchical generator stage, and injecting the constraint scenario into a next lower generator stage.
    Type: Application
    Filed: June 1, 2011
    Publication date: September 29, 2011
    Applicant: LSI CORPORATION
    Inventors: Sidhesh Patel, Prakash Bodhak
  • Trap-charge non-volatile switch connector for programmable logic
    Patent number: 8027198
    Abstract: A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: September 27, 2011
    Assignee: Halo LSI, Inc.
    Inventors: Tomoko Ogura, Seiki Ogura, Nori Ogura
  • Mosquito noise reduction filter in digital decoders
    Patent number: 8027383
    Abstract: A method for processing a compressed signal of digital video is disclosed. The method generally includes the steps of (A) generating a decompressed signal by decompressing the compressed signal of digital video, (B) generating a filtered signal by spatial filtering the decompressed signal, wherein the spatial filtering is arranged to reduce mosquito noise within the decompressed signal and (C) generating a video signal by adding synchronization information to the filtered signal, the synchronization information being suitable for synchronizing a video display to the filtered signal.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: September 27, 2011
    Assignee: LSI Corporation
    Inventors: Ho-Ming Leung, Suryanaryana M. Potharaju
  • SAS DOMAIN MANAGEMENT AND SSP DATA HANDLING OVER ETHERNET
    Publication number: 20110231571
    Abstract: A server application is executed on an active device within the SAS domain, the active device connected to a remote client via an Ethernet connection. At least one command is received from the remote client via the Ethernet connection. An Ethernet frame of the at least one command is converted to at least one SAS frame. The at least one SAS frame is routed via a SAS data path to a SAS target device connected to the active device, the SAS target device corresponding to a field of the command.
    Type: Application
    Filed: September 30, 2010
    Publication date: September 22, 2011
    Applicant: LSI CORPORATION
    Inventors: Mandar Dattatraya Joshi, Kaushalender Aggarwal, Saurabh Balkrishna Khanvilkar
  • Luminaire and Methods of Use
    Publication number: 20110228531
    Abstract: A lighting apparatus having a base member and a directional member are shown and described. The base member includes a first surface having a plurality of reflective elements extending therefrom. The base member also including a plurality of openings arranged in a pattern. Each openings is configured to receive a respective light source. The directional member has a portion of a reflective surface positioned relative to at least one opening to reflect light radiating from a lighting source disposed within the opening towards a portion of at least one of the reflective elements extending from the base member.
    Type: Application
    Filed: June 1, 2011
    Publication date: September 22, 2011
    Applicant: LSI Industries, Inc.
    Inventors: John D. Boyer, James G. Vanden Eynden
  • CRYPTOGRAPHIC PROCESSING USING A PROCESSOR
    Publication number: 20110231673
    Abstract: In one embodiment, a cryptography processor compatible with the Advanced Encryption Standard (AES) for encrypting and decrypting has a memory storing each element of an AES State, normally 8-bit long, in a corresponding memory space that is at least 9 bits long. Using the larger memory spaces, the processor performs modified AES transformations on the State. A modified column-mixing transformation uses bit-shifting and XOR operations, thereby avoiding some multiplications and modulo reductions and resulting in some 9-bit State elements. A modified byte-substitution transformation uses a 512-element look-up table to accommodate 9-bit inputs. The modified byte-substitution transformation is combined with a modified row-shifting transformation. The memory has data registers each holding four State elements.
    Type: Application
    Filed: October 8, 2010
    Publication date: September 22, 2011
    Applicant: LSI CORPORATION
    Inventors: Dmitriy Vladimirovich Alekseev, Alexei Vladimirovich Galatenko, Aleksey Alexandrovich Letunovskiy, Alexander Markovic, Andrey Anatolevich Nikitin
  • Detection of moving interlaced text for film mode decision
    Patent number: 8023041
    Abstract: A method for detecting moving interlaced text in a video sequence originating through telecine is disclosed. The method generally includes the steps of (A) checking a motion condition of a current block in a current field in the video sequence for motion both (i) from a previous field in the video sequence to the current field and (ii) from the current field to a next field in the video sequence, (B) checking an artifact condition of the current block for a plurality of symmetric interlaced artifacts in both (i) a forward temporal direction and (ii) a backward temporal direction and (C) asserting a block motion indicator for the current block if all of (i) the motion condition is true and (ii) the artifact condition is true.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: September 20, 2011
    Assignee: LSI Corporation
    Inventors: Yunwei Jia, Lowell L. Winger
  • External regulator reference voltage generator circuit
    Patent number: 8022684
    Abstract: Disclosed is an external regulator reference voltage generator circuit that precisely controls the supply voltage applied to core logic to optimize the operational characteristics of the core logic 120 without using excessive power. An adaptive voltage and scaling optimization circuit 124 is used to detect the operating parameters of the core logic 120 and generate a voltage control signal to control a reference voltage regulator. The reference voltage regulator generates a regulator reference voltage in response to the voltage control signal that controls an external regulator which, in turn, generates the supply voltage.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: September 20, 2011
    Assignee: LSI Corporation
    Inventor: Ricky F. Bitting
  • Multimode block cipher architectures
    Patent number: 8023644
    Abstract: An architecture for a block cipher, where the architecture includes functional units that are logically reconfigurable so as to be able to both encrypt clear text into cipher text and decrypt cipher text into clear text using more than one block cipher mode based on at least one of advanced encryption standard and data encryption standard.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: September 20, 2011
    Assignee: LSI Corporation
    Inventors: Anatoli A. Bolotov, Mikhail I. Grinchuk, Lav D. Ivanovic, Paul G. Filseth, Anton I. Sabev
  • Trap-charge non-volatile switch connector for programmable logic
    Patent number: 8023326
    Abstract: A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: September 20, 2011
    Assignee: Halo LSI, Inc.
    Inventors: Tomoko Ogura, Seiki Ogura, Nori Ogura
  • Method characterizing materials for a trench isolation structure having low trench parasitic capacitance
    Patent number: 8021955
    Abstract: Provided are methods and composition for forming a multi-layer isolation structure on an integrated circuit substrate. A process can include selecting a lower dielectric material for the lower dielectric layer and selecting an upper dielectric material for the upper dielectric layer. A range of effective dielectric constants that correspond to the thicknesses the lower and upper dielectric materials are selected. A range of thicknesses for each of the lower and upper dielectric layers are determined from a range of acceptable dielectric constants using information indicating an effective dielectric constant corresponding to thicknesses of the materials for both the lower upper dielectric layers, enabling the formation of the multi-layer isolation structure.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: September 20, 2011
    Assignee: LSI Logic Corporation
    Inventors: Venkatesh P. Gopinath, Arvind Kamath, Mohammad R. Mirabedini, Ming-Yi Lee