Abstract: A memory operative to provide multi-port functionality includes multiple single-port memory cells forming a first memory array. The first memory array is organized into multiple memory banks, each of the memory banks comprising a corresponding subset of the single-port memory cells. The memory further includes a second memory array including multiple multi-port memory cells and is operative to track status information of data stored in corresponding locations in the first memory array. At least one cache memory is connected with the first memory array and is operative to store data for resolving concurrent read and write access conflicts in the first memory array.

Abstract: Certain embodiments of the present invention are improved turbo-equalization methods for decoding encoded codewords. In one embodiment, in global decoding iteration i, the magnitude values of all decoder-input LLR values (Lch) are adjusted based on the number b of unsatisfied check nodes in the decoded codeword produced by global iteration i?1. The improved turbo-equalization methods can be used as the sole turbo-equalization method for a given global decoding session, or interleaved with other turbo-equalization methods.

Abstract: A digital signal processing architecture supporting efficient coding of memory access information is provided. In an example embodiment, a digital signal processor includes an adjustment value register to store an initial adjustment value and a succeeding adjustment value. The digital signal processor may also include an address generator circuit to retrieve an instruction including a memory address value that is greater than N, and a further instruction including a further memory address value that is less than or equal to N. In addition, the digital signal processor may include a memory, which includes a high bank address space defined by memory locations that are uniquely identified with memory address values greater than N. The address generator circuit may access the high bank address space, using initial adjustment value and the memory address value, or using the succeeding adjustment value and the further memory address value.

Abstract: Storage array operations, such as code downloads and other operations of the type that cause loss of access to portions of the storage array, are managed in a manner that preserves access to other portions of the storage array so that other storage array operations, such as data synchronization, can continue.

Abstract: A pad structure and passivation scheme which reduces or eliminates IMC cracking in post wire bonded dies during Cu/Low-k BEOL processing. A thick 120 nm barrier layer can be provided between a 1.2 ?m aluminum layer and copper. Another possibility is to effectively split up the barrier layer, where the aluminum layer is disposed between the two barrier layers. The barrier layers may be 60 nm while the aluminum layer which is disposed between the barrier layers may be 0.6 ?m. Another possibility is provide an extra 0.6 ?m aluminum layer on the top barrier layer. Still another possibility is to provide an extra barrier layer on the top-most aluminum layer, such that a top barrier layer of 60 nm is provided on a 0.6 ?m aluminum layer, followed by another harrier layer of 60 nm, another aluminum layer of 0.6 ?m and another barrier layer of 60 nm.

Abstract: Methods and systems for processing a second request before processing of a first request has completed. The first request is associated with a first flow control credit type, and the second request is associated with a second flow control credit type. After a period of time, the second request is selected for processing based on the first flow control credit type and the second flow control credit type.

Abstract: The present disclosure provides a methodology by which disk level access for storage drives of a storage array may be highly secured based on permission settings applied to the driver interface of the storage drives. Based on specific set of access rules, a security component applies security profiles to permit/deny access to an individual storage drive, sets the storage drive with a first security level, monitors for a triggering event, and sets the storage drive to a second (more restrictive) security access level in response to the triggering event. In addition, the security component generates an alert in response to the triggering event. Thus, disk level access permissions are applied at a driver interface layer and permissions are applied based on administrator-defined policies. The present disclosure provides for complete lock-down of data permissions, management and/or restriction of IO loads, and protection of “read-only” data integrity from overwrites.

Abstract: A failed link is detected between a first SAS expander and a device. A data transfer of the first SAS expander connected to the device via the failed link is re-routed to a second SAS expander connected to the device via a functional link. The first SAS expander is connected to the SAS expander via the phys of the first SAS expander and the phys of the second SAS expander for inter-expander communications.

Abstract: The present invention is directed to a system and method for a quality assurance tool generating test plans and identifying new test requirements for a new version of a product. Old versions of the product may be previously tested and test plan documents associated with previously tested versions of the product may be stored in a database. The database may store test plans, test configurations, test scopes, and the like for previously tested versions of the product. Product design requirements may be determined based on received customer desired features for the new version. The database may be updated by adding new tests for new features of the new version. A test plan document for the product may be generated based on the updated database. The generated test document may be verified through automatically generating a general test plan for the new version of the product by querying updated database with the product design requirements.

Abstract: In one embodiment, a hard-disk drive system performs fly-height control using a read-back mode and a loop-back mode. The read-back mode measures first and second harmonics pre-recorded on the medium and divides the first measurement by the second to obtain a read-back mode harmonic ratio. The loop-back mode measures the same first and second harmonics; however, the harmonics are provided by a write precompensation circuit rather than the medium. Further, the loop-back mode measurements are performed using asynchronous sampling to address aliasing and quantization errors. The first measurement is divided by the second to generate a loop-back harmonic ratio. In logarithm domain, the loop-back ratio is subtracted from the read-back mode ratio to remove environment-induced variations in the read path electronic circuits. The resulting harmonic ratio is subtracted from an initial harmonic ratio determined, for example, during manufacturing, to determine how much the harmonic ratio has changed.

Abstract: An improvement to an integrated circuit of a type having a test enable line for enabling an electrical test of the integrated circuit only when the test enable line is at a logical high value, and output lines that are only used during the electrical test of the integrated circuit, where the improvement is a switch circuit for disabling a state change in the output lines when the test enable line is at a logical low value. In this manner, the output lines do not switch during functional use of the integrated circuit, and cannot be aggressors on the data signals that are carried by the data lines that are used during the functional use of the integrated circuit. In addition, these non-switching output lines can act as guard traces that run between the data lines, further electrically isolating the data lines from one another. Further, because they do not switch during functional use of the integrated circuit, the overall power consumption of the integrated circuit is reduced.

Abstract: An adaptive input/output (I/O) scheduler for storage arrays is disclosed. In one embodiment, a method of a redundant array of independent disks (RAID) controller for deploying an optimal I/O scheduler type per a storage array configuration includes generating performance data by assessing respective performances of a plurality of I/O scheduler types on different RAID level test volumes with at least one I/O pattern generated internally within a storage subsystem which comprises the RAID controller. The method also includes storing the associativeness of the performance data with respect to a particular I/O scheduler most suited for a given I/O workload to a nonvolatile memory of the RAID controller. The method further includes deploying an optimal one of the plurality of I/O scheduler types and at least one performance parameter for at least one subsequent I/O operation associated with the storage subsystem based on the performance data.

Abstract: A system for sending large Command Descriptor Block (CDB) structures in a serial attached SCSI (SAS) controller includes a CDB Transmit Block, a CDB Memory, a Context Memory, a Direct Memory Access (DMA) Queue, a Transmit DMA Engine, and a SAS Interface. The CDB Transmit Block receives one or more Message Frames. If the CDB is small (32 bytes or less), the CDB Transmit Block reads data from the Message Frame and transmits a SAS Command Frame over the SAS interface. If the CDB is large (33 bytes or more), the CDB Transmit Block places a large CDB entry into the DMA Queue. The Transmit DMA Engine receives the large CDB entry from the DMA queue, utilizes an address pointer from the Message Frame to the CDB Memory to fetch large CDB information into a DMA buffer, and transmits a SAS Command Frame over the SAS interface.

Abstract: A clock-switching circuit having at least two inputs for receiving at least two different clock sources, an output for providing a selected one of the clock sources, and a switch for selecting the one of the inputs to provide on the output, the switch including elements that, prevent the providing of a truncated version of any of the clock sources on the output, always provide a clock signal on the output, and always maintain phase alignment and pulse ratio of the clock sources on the output.

Abstract: An electronic device includes an active layer located over a substrate with the active layer having a logic circuit and an eDRAM cell. The electronic device also includes a first metallization level located over the active layer that provides logic interconnects and metal capacitor plates. The logic interconnects are connected to the logic circuit and the metal capacitor plates are connected to the eDRAM cell. The electronic device additionally includes a second metallization level located over the first metallization level that provides an interconnect connected to at least one of the logic interconnects, and a bit line that is connected to the eDRAM cell. A method of manufacturing an electronic device is also included.

Abstract: The present invention provides an architecture for a platform, which includes (1) gates located in a central area of a die for supporting an application layer; (2) a SerDes region located at one side of the die for holding at least one SerDes device; (3) a Link Layer Controller region, located adjacent the SerDes region and between the SerDes region and the gates, for supporting the at least one SerDes device; and (4) at least one RAM array for supporting the at least one SerDes device, the at least one RAM array being located at least one of adjacent the gates or between the gates and the Link Layer Controller region.

Abstract: An embodiment of the present invention is disclosed to include a SATA Switch allowing for access by two hosts to a single port SATA device Further disclosed are embodiments for reducing the delay and complexity of the SATA Switch.

Abstract: An electronic device includes an integrated circuit (IC) package attached to a substrate and a heat sink attached to the IC package. Additionally, the electronic device also includes a film having an electric conductivity and contacting the heat sink and the IC package and extending to the substrate to provide a grounding connection for the heat sink. A method of manufacturing an electronic device includes connecting an IC package to a substrate, coupling a heat sink to the IC package and depositing a film having an electric conductivity and contacting the heat sink and the IC package and extending to the substrate to provide a grounding connection for the heat sink.

Abstract: A device for holding and positioning an optic, such as a refractive lens, over a light source such as a light emitting diode. The refractive lens is frustum-shaped with an upper light-exiting end having an upper rim, a lower light-entering end, and a conical sidewall that tapers from the upper rim to the lower end. The device has a channel including a base and first and second sidewalls extending from the opposed side edges of the base, and further having one or more optic holding positions. The optic holding position includes an aperture formed in the base that is configured to receive the conical sidewall of the optic, and an aperture formed in a portion of each sidewall, adjacent the aperture in the base, for retaining a portion of the upper rim of the optic lens. The aperture can include a slot opening through which a portion of the upper rim of the optic lens at least partially extends.

Abstract: Methods and systems for improving communication throughput of a link between SAS/SATA devices. The link, initially established at a first signal rate, is one of a SATA link and a SAS link. A SAS/SATA device increments one of the at least one counter based on an error sensed on the link. Based on the at least one counter, the SAS/SATA device determines whether to maintain the first signal rate. The link is re-established at a second signal rate based on the determination such that the second signal rate is lower than the first signal rate.