Abstract: Airbag inflators employ gas generating compositions formed from a mixture of fuels and a mixture of oxidizers and preferably mica at levels of 1 to 5% by weight. The gas generant composition contains a primary and secondary fuel. The primary fuel is a guanidine compound, preferably guanidine nitrate. The secondary fuel is selected from tetrazoles, triazoles and mixtures thereof at levels of 5% by weight or less of the total gas generant composition. The oxidizer system is a mixture of at least two components selected from the group consisting of transition metal oxides, alkali metal nitrates and alkaline earth metal nitrates. The novel gas generants yield inflating gases having a reduced content of undesirable gases such as nitrous oxides and carbon monoxide.

Abstract: A method of manufacturing a device containing a key is disclosed. The method generally includes the steps of (A) fabricating a chip comprising a random number generator, a nonvolatile memory and a circuit, (B) applying electrical power to the chip to cause the random number generator to generate a signal conveying a sequence of random numbers, (C) commanding the chip to program a first arbitrary value among the random numbers into the nonvolatile memory, wherein the device is configured such that the first arbitrary value as stored in the nonvolatile memory is unreadable from external to the device and (D) packaging the chip.

Abstract: Apparatus, systems, and methods for testing SAS cables by applying a signal to one end of a SAS cable, receiving the signal from another end of the SAS cable, and generating an output of information relating to the testing. The testing apparatus may test one or more configuration characteristic of the SAS cable, including, for example a crossover status, a polarity status of transmit (“TX”) wires, and a polarity status of receive (“RX”) wires.

Abstract: Debugging a simulation of a circuit core uses a pattern recorder, a pattern player and a pattern checker to record input stimuli provided to a first core, record output generated by the first core due to the input stimuli, provide the recorded input stimuli to a second core, and determine whether output generated by the second core due to the recorded input stimuli matches the recorded output generated by the first core due to the input stimuli.

Abstract: An adaptive clock recovery (ACR) subsystem processes an input phase signal indicative of jittery packet arrival times to generate a relatively smooth and bounded output phase signal that can be used to generate a relatively stable recovered clock signal. The input phase signal is also processed to detect and measure step-delays corresponding, for example, to path changes in the network routing of the packets. Step-delay pre-compensation is performed, in which the input phase signal is phase-adjusted, upstream of the ACR subsystem, based on the sign and magnitude of each detected step-delay. As a result, the ACR subsystem is substantially oblivious to the existence of such step-delays.

Abstract: An adaptive clock recovery (ACR) system has a first closed-loop control processor (e.g., a first proportional-integral (PI) processor) that processes an input phase signal indicative of jittery packet arrival times to generate a mean phase reference. The input phase signal is compared to the mean phase reference to generate delay-offset values that are indicative of the delay-floor corresponding to the packet arrival times. The mean phase reference and the delay-offset values are used to generate offset-compensated phase values corresponding to the delay-floor. The ACR system also has a second closed-loop control processor (e.g., a second PI processor) that smoothes the offset-compensated phase values to generate an output phase signal that can be used to generate a relatively phase stable recovered clock signal, even during periods of varying network load that adversely affect the uniformity of the packet arrival times.

Abstract: A method for reduced memory and bandwidth motion adaptive video deinterlacing is disclosed. The method generally includes the steps of (A) generating a frame by deinterlacing a current field in a first of a plurality of modes, (B) generating the frame by deinterlacing using both of the current field and an opposite-parity field in a second of the modes and (C) generating the frame be deinterlacing using all of the current field, the opposite-parity field and another field in a third of the modes, wherein the method uses at least two of the modes.

Abstract: Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a latch based analog to digital converter is disclosed that includes a first interleave with a set of comparators, a selector circuit and a latch. The set of comparators is operable to compare an analog input with respective reference voltages, and is synchronized to a clock phase. The selector circuit is operable to select an output of one of the set of comparators based at least in part on a selector input. A first interleave output is derived from the selected output. The latch receives a second interleave output from a second interleave and is transparent when the clock phase is asserted. The selector input includes an output of the latch.

Abstract: Various embodiments of the present invention provide systems and methods for providing a corrected dibit signal. As an example, various embodiments of the present invention provide dibit correction circuits. Such dibit correction circuits include a dibit sample buffer, a maximum sample detector circuit, a side sample detector circuit, and a dibit correction circuit. The dibit sample buffer includes a plurality of samples of an uncorrected dibit signal. The maximum sample detector circuit identifies a maximum sample of the plurality of samples of the uncorrected dibit signal, and the side sample detector circuit identifies a first side sample prior to the maximum sample on the uncorrected dibit signal and a second side sample following the maximum sample on the uncorrected dibit signal.

Abstract: Described embodiments provide for end-of-life (EOL) checking for NAND flash devices. An exemplary implementation of a computing environment comprises at least one NAND data storage device operative to store one or more data elements. In the illustrative implementation, the EOL data processing and storage management paradigm allows for the storage of data according using a selected EOL enforcement algorithm that can utilize current and/or historical correction levels. The NAND data storage EOL checking module can be operable to cooperate with one or more NAND data store components to execute one or more selected EOL operations to protect stored data.

Abstract: Housings are described that include snap fittings or connections that can be placed on portions of the housing to allow assembly of the housing in the field, without the need for assembly tools or welding. Reduced assembly time and cost, as well as the reduction/elimination of tooling costs for assembly tools and/or associated hardware can therefore be realized. Exemplary embodiments of the present disclosure can include a snap fitting with first and second portions, e.g., male and female portions, including a portion having a tab or clip punched out of a sheet and including a holding protrusion or portion, and another portion having an aperture or depression configured and arranged to receive and be held by the holding portion. Preferred embodiments can be utilized as light pole base covers.

Abstract: A method of verifying integrated circuit designs, by constructing a series of atomic generators in a staged, hierarchical order, applying a lowest of the hierarchical generator stages to device level test cases of the verification process, applying a highest of the hierarchical generator stages to system level test cases of the verification process, reusing code written for and used in the lowest hierarchical generator stage in a next higher generator stage, creating a constraint scenario in the highest hierarchical generator stage, and injecting the constraint scenario into a next lower generator stage.

Abstract: In one embodiment, a (hard-drive) read channel has a phase detector used in a timing recovery loop. The phase detector utilizes the sign bit and confidence value from a received log-likelihood ratio (LLR) signal to generate a mean value. The mean value is convolved with a partial response target to generate an estimated timing error signal. When implemented in a hard-drive read channel, the phase detector allows for timing recovery with lower loss-of-lock rates.

Abstract: A ROM comprises several bit output lines and X address decode lines, and stores a data set. Each address decode line stores a unique data word. Addresses in the data set that have the same data word are mapped by the decoder to the same address decode line. Each address decode line is electrically connected to a bit output line as determined by the data set. An initial design of the ROM uses N connecting devices to respectively electrically connect N of the address decode lines to a bit output line. If N exceeds X/2, then an optimization process is performed. The optimization process involves electrically disconnecting each address decode line that was connected to the bit output line, and electrically connecting each address decode line that was not connected to the bit output line. The output of the bit output line is then run through a logical inverter to provide the correct output data bit.

Abstract: A scan clock generator includes a clock signal input for receiving a clock signal, a scan shift mode signal input for receiving a scan shift mode signal, and a sequence controller coupled to the clock signal input for gating a selected number of clock signal pulses at a time to generate a sequence of nonconcurrent scan clock signals at separate outputs respectively in response to a first state of the scan shift mode signal.

Abstract: A method of breaking a redundant array of independent disks level 1 (RAID 1 ) for preservation of data integrity is disclosed. In one embodiment, a method for breaking a RAID 1 to preserve data integrity of the RAID 1 includes breaking a redundancy of the RAID 1 when a size of data stored in the RAID 1 exceeds a storage capacity of the RAID 1, where the RAID 1 includes a first disk and a second disk mirroring the first disk. Further, the method includes writing a portion of the data exceeding the storage capacity of the RAID 1 to the second disk, and restoring the redundancy of the RAID 1 by using two additional disks implemented to the RAID 1.

Abstract: A lighting apparatus having a pivotable light cartridge for positioning and directing the light output of a plurality of light sources, the light cartridge including an elongated base oriented along the longitudinal axis, a pivot at the opposed first and second ends of the light cartridge along the longitudinal axis, a plurality of light sources, and an longitudinal wall extending from the lateral edge of the base, the wall including a plurality of spaced-apart, radially-extending ribs, each having a distal edge. A rotatable worm gear having a helical thread is positioned in mechanical engagement with a portion of the distal edges of the plurality of ribs, so that rotation of the worm gear with a hand tool effects pivoting of the light cartridge along the longitudinal axis.

Abstract: One embodiment is a method for booting a bootable virtual storage appliance on a virtualized server platform. One such method comprises: providing a virtual storage appliance on a server platform, the virtual storage appliance configured to manage a disk array comprising a plurality of disks, and wherein at least one of the disks comprises a hidden boot partition having a boot console; powering up the server platform; loading boot code on the server platform; loading the boot console from the hidden boot partition; and the boot console loading boot components for a virtualization environment.

Abstract: A method of grounding a heat spreader/stiffener to a flip chip package comprising the steps of attaching an adhesive film to a substrate and attaching a stiffener to the adhesive film. The adhesive film may have a number of first holes corresponding with a number of grounding pads on the substrate. The grounding pads may be configured to provide electrical grounding. The stiffener may have a number of second holes corresponding with the number of first holes of the adhesive film and number the grounding pads of the substrate. The grounding pads are generally exposed through the first and the second holes.

Abstract: A memory interface physical layer macro including one or more embedded input/output (I/O) buffers, one or more memory interface hardmacros and control logic. The one or more embedded input/output (I/O) buffers support a plurality of I/O supply voltage levels. The one or more memory interface hardmacros are coupled to the one or more embedded I/O buffers. The control logic controls the one or more hardmacros and the one or more I/O buffers.