Abstract: A wafer edge defect inspection method and apparatus for use in an integrated circuit fabrication system includes an image capturing device for capturing images of the edges of wafers, a database in which the images are stored and accessible for analysis and a computer for analyzing the images of one or more wafer edges to locate edge defects and for evaluating the performance of the fabrication system. The inspection and data storage are performed automatically. The database storage enables detailed analysis of many wafers and fabrication process steps.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes an analog to digital converter, a digital interpolation circuit, a phase error circuit, and a phase adjustment control circuit. The analog to digital converter samples an analog data input at a sampling phase governed at least in part by a coarse control, and provides a series of digital samples. The digital interpolation circuit interpolates between a subset of the series of digital samples based at least in part on a fine control. The phase error circuit calculates a phase error value. The phase adjustment control circuit is operable to determine the coarse control and the fine control based at least in part on the phase error value.

Abstract: A method for decoding a bitstream comprising the steps of (A) generating a first field picture in response to a frame picture of a first bitstream, (B) generating a second field picture in response to the frame picture of the first bitstream and (C) generating a second bitstream containing the first field picture and the second field picture.

Abstract: Electronic circuitry and methods are disclosed for monitoring a portion of a write driver, for example, a steady state value of a write driver of a hard disk drive preamplifier. Based on a result of the monitoring, a condition, such as a fault, can be detected in the write driver. For example, apparatus for monitoring a write driver of a disk drive system comprises a comparator circuit coupled to an output of the write driver and configured to compare a value present at the output of the write driver with a reference value such that at least one condition associated with the write driver is detectable as a result of the comparison of the write driver output value and the reference value.

Abstract: Methods and devices for reading data from a plurality of storage devices belonging to a plurality of spans and checking consistency (e.g., XOR parity check) of data belonging to each span independently of another span in one embodiment. Methods and devices for reading data from a plurality of stripes and checking consistency of the data from the plurality of stripes in another embodiment.

Abstract: A system for, and method of, reducing the generation of inconsequential violations resulting from timing analyses and an electronic design automation (EDA) tool incorporating the system or the method. In one embodiment, the system includes: (1) a timing violation identifier configured to identify at least some timing violations in a circuit based on a timing analysis, (2) an unsensitizable path identifier configured to identify at least some unsensitizable paths in the circuit and (3) a repair list generator coupled to the timing violation identifier and the unsensitizable path identifier and configured to generate a repair list based on both the at least some timing violations and the at least some unsensitizable paths.

Abstract: Various embodiments of the present invention provide systems and methods for using data equalization. For example, various embodiments of the present invention provide storage devices that include a semiconductor device having an equalization unit and a digital-to-analog converter, a read/write head assembly located in close proximity to the semiconductor device, and a control unit located less proximate to the read/write head assembly than the semiconductor device.

Abstract: A method to analyze timing in a circuit, generally including (A) simulating reception of an input signal and a clock signal at a first flip-flop, wherein (i) the input signal has a latest transition, (ii) the input signal arrives through a first path and (iii) the clock signal has an active edge, (B) calculating a value of a time difference between the latest transition and the active edge, (C) calculating a delay between the active edge and the latest transition appearing in an output signal, wherein (i) the delay is based on a model responding to the value, (ii) the model characterizes a clock-to-output delay as a function of the time difference and (iii) the characterization covering a range of values, (D) calculating an arrival time of the latest transition at a second flip-flop through a second signal path and (E) storing the arrival time in a recording medium.

Abstract: In one embodiment, a tape measure having a tape, housing, and an input, has an OLED strip overlaid on top of the tape. The housing contains a programmable controller and a rolled-up portion of the tape. A specified fraction of the length of the linear target is provided to the controller using the input. The tape may be extracted from the housing to generate an exposed portion of the tape corresponding to the total length of a linear target. The controller receives information indicative of the total length of the linear target. The controller controls the OLED strip to show, i.e., light up along the tape, a fractional portion corresponding to the specified fraction of the linear target.

Abstract: An arbitration logic including one or more modular priority encoders. Each modular priority encoder includes a first logic circuit, a comparator circuit, a second logic circuit, and an encoder circuit. The first logic circuit may be configured to generate a first output signal in response to a plurality of request signals. The comparator circuit may be configured to compare all possible pairs of a plurality of priority signals. The second logic circuit may be configured to generate a control signal in response to (i) the plurality of request signals and (ii) a result of comparing all possible pairs of the plurality of priority signals. The encoder circuit may be configured to generate a second output signal in response to the control signal.

Abstract: Methods and apparatus for distributing Redundant Array of Independent Disks (RAID) storage management to one or more Serial Attached SCSI (SAS) expanders in a SAS domain. A RAID set comprises a set of one or more SAS expanders coupled to communicate with one another to process I/O requests directed to a RAID logical volume of the RAID set. The RAID logical volume is distributed over portions of each of multiple storage devices. Each SAS expander of the RAID set is coupled to one or more of the multiple storage devices. Each SAS expander of the RAID set processes a corresponding portion of a received I/O request directed to the RAID logical volume. A master SAS expander of the RAID set receives and aggregates the status information from each of the SAS expanders of the RAID set and returns a completion status to the requesting SAS initiator.

Abstract: Methods and apparatus are provided for soft demapping and intercell interference mitigation in flash memories. In one variation, a target cell in a flash memory device capable of storing at least two data levels, s, per cell is read by obtaining a measured read value, r, for at least one target cell in the flash memory; obtaining a value, h, representing data stored for at least one aggressor cell in the flash memory; selecting one or more probability density functions based on a pattern of values stored in at least a portion of the flash memory, wherein the probability density functions comprises pattern-dependent disturbance of one or more aggressor cells on the at least one target cell in the flash memory; evaluating at least one selected probability density function based on the measured read value, r; and computing one or more log likelihood ratios based on a result of the evaluating step.

Abstract: Methods and apparatus are provided for programming multiple program values per signal level in flash memories. A flash memory device having a plurality of program values is programmed by programming the flash memory device for a given signal level, wherein the programming step comprises a programming phase and a plurality of verify phases. In another variation, a flash memory device having a plurality of program values is programmed, and the programming step comprises a programming phase and a plurality of verify phases, wherein at least one signal level comprises a plurality of the program values. The signal levels or the program values (or both) can be represented using one or more of a voltage, a current and a resistance.

Abstract: An apparatus comprising a first circuit, a second circuit and a disc. The first circuit may be configured to (i) extract video data as data blocks from an input signal and (ii) perform error correction on the data blocks with a delta syndrome based iterative Reed-Solomon decoding. The second circuit may be configured (i) to decode corrected video data into a video format in a first state, (ii) encode the corrected video data in a second state and (iii) share an external memory between the first circuit and the second circuit. The disc may be configured to store encoded video data in the second state.

Abstract: A circuit for implementing elliptic curve and hyperelliptic curve encryption and decryption operations, having a read only memory with no more than about two kilobytes of accessible memory, containing first programming instructions. An arithmetic logic unit has access to second programming instructions that are resident in a gate-level program disposed in the arithmetic logic unit, and is operable to receive data from no more than one input FIFO register. A microcontroller has no more than about two thousand gates, and is adapted to read the first programming instructions from the read only memory, send control signals to the arithmetic logic unit, and receive flags from the arithmetic logic unit. The arithmetic unit reads the third programming instructions, selectively performs elliptic curve and hyperelliptic curve encryption and decryption operations on the data according to the second programming instructions and the microcontroller, and sends output to no more than one output FIFO register.

Abstract: An embodiment of the present invention includes a communication system configured to conform to SATA or SAS standards and causing communication between one or more hosts and a SATA device. The communication system includes a communication device adapted to generate debug information incorporated through one or more links using an analyzer to identify problems associated with the communication system.

Abstract: An apparatus having a first circuit, a second circuit and a third circuit. The first circuit may be configured to (i) demultiplex a multimedia stream having one or more video and audio streams and (ii) generate one or more video signals and one or more audio data signals in response to demultiplexing the multimedia stream. The multimedia stream may be independent of embedded time stamps. The second circuit may be configured to (i) decode the one or more video data signals and the one or more audio data signals and (ii) generate a video current time signal for each decoded video signal and an audio current time signal for each decoded audio signal. The third circuit may be configured to synchronize the playback of each decoded audio signal and each decoded video signal with the video current time signal and the audio current time signal.

Abstract: An apparatus including a test circuit, an output circuit and a control circuit. The test circuit may be configured to generate test data in response to one or more test vectors. The output circuit may be configured to present data in a first mode and prevent presentation of data in a second mode. The output circuit may be configured to switch between the first mode and the second mode in response to a control signal. The control circuit may be configured to generate the control signal according to predetermined criteria for protecting secure data within the apparatus while allowing the test data to be presented.

Abstract: In a receiver, an AC-coupling solution uses a fully integrated circuit for simultaneously providing both baseline wander compensation and common-mode voltage generation. Usefully, an integrated capacitor is placed between the receiver input pin and the input buffer, and a high resistive impedance element is connected to the internal high-speed data node after the capacitor. An on-chip voltage generation and correction circuit is connected to the other side of the impedance element to generate a common-mode voltage, and to provide dynamic, fine adjustment for the received data voltage level. The voltage correction circuit is controlled by the feedback of data detected by the clock and data recovery unit (CDRU) of the receiver. The feedback data passes through a weighting element, wherein the amount of feedback gain is adjustable to provide a summing weight and thereby achieve a desired BLW compensation.

Abstract: A method for motion adaptive video deinterlacing is disclosed. The method generally includes the steps of (A) in a first plurality among a plurality of modes, generating a frame by deinterlacing a current field using a plurality of memory bandwidth configurations and (B) in a second plurality among the modes, generating the frame by deinterlacing the current field using a plurality of linestore configurations.