Abstract: Multiple hardware accelerators can be used to efficiently perform processes that would otherwise be performed by general purpose hardware running software. The software overhead and bus bandwidth associated with running multiple hardware acceleration processes can be reduced by chaining multiple independent hardware acceleration operations within a circuit card assembly. Multiple independent hardware accelerators can be configured on a single circuit card assembly that is coupled to a computing device. The computing device can generate a playlist of hardware acceleration operations identifying hardware accelerators and associated accelerator options. A task management unit on the circuit card assembly receives the playlist and schedules the hardware acceleration operations such that multiple acceleration operations may be successively chained together without intervening data exchanges with the computing device.

Abstract: Various embodiments of the present invention provide systems and methods for equalizing an input signal. For example, various embodiments of the present invention provide a method for performing equalization in a storage device. Such methods include providing an equalizer circuit that is governed by a target value, and a filter circuit that is governed by a filter coefficient. An initial value is provided to the equalizer circuit as the target value, and an overall target based at least in part on the initial value and the filter coefficient is calculated. An updated value is calculated based on the overall target, and the updated value is provided to the equalizer circuit as the target value.

Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate status signals and an error signal in response to accessing a storage medium. The error signal provides a first value based on an accuracy of accessing the storage medium. The second circuit may be configured to offset the first value of the error signal to a second value to increase the accuracy of accessing said storage medium. The status signals include one or more of a data signal and a differential signal. In a first mode, an offset signal is generated in response to the data signal. In a second mode, the offset signal is generated in response to the differential signal.

Abstract: Methods and systems for recovering data utilize a command line interface of a data-processing system, run by an operating system such as Linux, Unix, DOS, Windows, Mac and the like, to recover and manage inadvertently deleted data. Desired data such as files, folders, and the like can be initially identified from a command line interface. The desired data can then be automatically saved in a memory location of the data-processing system, in response to identifying the desired data from the command line interface. The data can then be automatically recovered from the memory location of the data-processing system for display within the command line interface, if the desired data is inadvertently deleted. Additionally, a user can be permitted to specify a plurality of recycling rules presented through a graphical user interface dialog or other graphical user interface device.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to analyze an audio-video data stream to determine watermark appropriate information for the audio-video data stream. The second circuit may be configured to communicate the watermark appropriate information either in-band with or out-of-band from a bit stream communicating the audio-video data.

Abstract: An apparatus includes a first semiconductor die and at least one further semiconductor die. A substrate is attached to the first die and the further die and has an electrical interconnect pattern that interconnects contacts on the first die with respective contacts on the further die. Features of the interconnect pattern have positions on the substrate with smaller tolerances relative to positions of the contacts on the first die than to positions of the contacts on the further die.

Abstract: One embodiment is a method for installing a virtual storage appliance on a host server platform. One such method comprises: providing an installation package to a host server platform, the installation package comprising an installation script for installing an I/O virtual machine (IOVM), an IOVM boot console, and an IOVM management module; running the installation script to create a hidden boot partition on a boot disk and copy the IOVM boot console and the IOVM management module to the hidden boot partition; rebooting the host server platform; loading the IOVM boot console and the IOVM management module from the hidden boot partition; configuring a disk array via the IOVM management module; for each disk in the array, creating a hidden boot partition and replicating the IOVM boot console and the IOVM management module; and installing a virtual storage environment using the IOVM boot console as a storage driver.

Abstract: In one embodiment, a (hard-drive) read channel has a (DFIR equalization) filter, whose tap coefficients are adaptively updated. A reset controller monitors an (LLR) signal generated downstream of the filter to automatically determine when to reset the filter, e.g., by reloading an initial set of user-specified tap coefficients. For LLR values, the reset controller determines to reset the filter when the reset controller detects that too many recent LLR values have confidence values that are too low. When implemented in a hard-drive read channel, the reset controller can reset the filter one or more times during read operations within a sector of the hard drive.

Abstract: The present disclosure describes a systems and methods for dynamic storage tiering A method for dynamic storage tiering may comprise: creating a point-in-time copy of a virtual volume including a storage hot-spot; copying a virtual volume segment including the hot-spot from a first storage pool to a second storage pool; and reconfiguring a logical block address mapping of the virtual volume to reference the virtual volume segment copy in the second storage pool. A system for dynamic storage tiering may comprise: means for creating a point-in-time copy of a virtual volume including a storage hot-spot; means for copying a virtual volume segment including the hot-spot from a first storage pool to a second storage pool; and means for reconfiguring a logical block address mapping of the virtual volume to reference the virtual volume segment copy in the second storage pool.

Abstract: The invention relates to a method for computer signal processing data and command transfer over an interface and more particularly to a communication between peripheral firmware and a host processor or Basic Input/Output System (BIOS) on a Peripheral Component Interconnect (PCI) bus. In one embodiment, a device and method for reducing the load on the PCI Bus is described. In yet another embodiment, a device and method is described for constructing a variable length command block comprising message frames and aligning all message frames for a particular command block that are contiguous in memory.

Abstract: Embodiments include methods and systems for processing XML documents. One embodiment is a system that includes a method of efficiently processing XML documents received concurrently from a plurality of network connections in the form of streams of data. Other embodiments include systems configured to perform such processing of streamed XML documents. Other embodiments include systems and methods of efficiently performing document processing using digests for identifying XML document structure.

Abstract: Methods and systems for improving performance in a storage system utilizing snapshots are disclosed by using metadata management of snapshot data. Specifically, various metadata structures associated with snapshots are utilized to reduce the number of IO operations required to locate data within any specific snapshot. The number of IO operations are reduced by allowing the various metadata structures associated with the temporally current snapshot to locate data directly within any temporally earlier snapshot or on the original root volume.

Abstract: In one embodiment, a signal processing receiver has a branch-metric calibration (BMC) unit that receives (i) sets of four hard-decision bits from a channel detector and (ii) a noise estimate. The BMC unit has two or more update blocks (e.g., tap-weight update and/or bias-compensation blocks) that generate updated parameters used by a branch-metric unit of the channel detector to improve channel detection. The two or more update blocks generate the updated parameters based on (i) the sets of four hard-decision bits, (ii) the noise estimate, and (iii) bandwidth values. The bandwidth values for at least two of the two or more update blocks are selected such that they are different from one another. Selecting different bandwidth values may reduce the bit-error rate for the receiver over the bit-error rate that may be achieved by selecting the bandwidth values to be the same as one another.

Abstract: A method of encoding a binary source message u, by calculating x:=Au, calculating y:=B?x, resolving the equation Dp=y for p, and incorporating u and p to produce an encoded binary message v, where A is a matrix formed only of permutation sub matrices, B? is a matrix formed only of circulant permutation sub matrices, and D is a matrix of the form D = ( T 0 … 0 0 0 T … 0 0 … … … … … 0 0 … T 0 I I … I I ) where T is a two-diagonal, circulant sub matrix, and I is an identity sub matrix.

Abstract: An apparatus comprising a center error creation circuit and a center error offset injection circuit. The center error creation circuit may be configured to generate a center error signal in response to light from a main laser reflected from a surface of an optical disc. The center error offset injection circuit may be configured to (i) determine a value of the center error signal when a lens in a sled housing is at a mechanical center and (ii) generate an offset signal based upon the value. The center error offset injection circuit generally measures an average value of the center error signal over a predetermined amount of time when a lens suspension which holds the lens in place is in a mechanical equilibrium state.

Abstract: A configurable storage array controller can be configured to either a single-processor configuration or a multi-processor configuration by configuring a data bus switch system.

Abstract: A BISR mode and associated method for testing memory. All redundant elements of the memory including the ones which are not used are tested, and interaction between redundant elements of the memory and adjacent functional memory are checked. Repair information is used to repair the memory. In addition, redundant elements which are not needed to be used for repairing the memory are forced to be used, such as by faking defects to remap good elements with redundant elements.

Abstract: A method for transcoding from an H.264 format to a VC-1 format. The method generally comprises the steps of (A) decoding an input video stream in the H.264 format to generate a picture having a plurality of macroblock pairs that used an H.264 macroblock adaptive field/frame coding; (B) determining a mode indicator for each of the macroblock pairs; and (C) coding the macroblock pairs into an output video stream in the VC-1 format using one of (i) a VC-1 field motion compensation mode coding and (ii) a VC-1 frame motion compensation mode coding as determined from the mode indicator.

Abstract: Apparatus methods for capturing flow control errors in FIFO exchanges between producing and consuming circuits operating in different clock domains. Tag information at the start of an exchange is transferred to a synchronizing component before data of a transfer transaction is entered in the FIFO. The tag information is also associated with each unit of data transferred to the FIFO by the producing circuit. The synchronizing component verifies the each unit of data retrieved by the consuming circuit has the expected tag information associated therewith and signals an error is the tag information does not match. Thus an error by the producing circuit in entering too much or too little data for a transfer is detected before erroneous data is retrieved and processed by the consuming circuit.

Abstract: The optimal lanes of at least one SAS wide port for the data connection are discovered. The allowable lanes for the data connection within the SAS wide ports of each level of the SAS domain are specified. The specified allowable lanes for the data connection are checked. The data connection is created on the specified allowable lanes.