Abstract: In a high-speed serial link, an eye finder diagnostic circuit has improved performance by being on-chip with the existing capture latch(es) of a receive equalizer. The eye finder circuit employs an additional capture latch with its input tied to the same input node as the existing capture latch(es) of a receive equalizer. The additional capture latch has a clock input and reference voltage input. The clock input is adjusted through a phase interpolator (or variable delay line) while the reference voltage input is adjusted by a voltage generator. A digital post processing circuit then compares the output of the additional capture latch with the output of the other existing capture latch(es), in order to determine the receive eye opening. The horizontal eye opening is measured by changing the phase of the additional capture latch through the phase interpolator, while the vertical eye opening is measured by changing the reference voltage of the voltage generator of the additional capture latch.

Abstract: A system for updating management entities or devices in a computer system network with configuration change information from the devices being managed. The management entities are configured to discover, monitor and configure managed devices, such as storage systems, connected to the network. Preferably, the managed devices include a comparator which can track changes made to the managed device configuration or properties and report that change back to the various management entities. In this way, the management entities can keep track of the configurations of the various devices that they manage, even though they might not be responsible for issuing the configuration change. This can be accomplished even when managed devices developed by different manufacturers according to different standards or protocols are involved.

Abstract: A data-processing system and method are disclosed, which include a cached processor for processing data, and a plurality of memory components that communicate with the cached processor. The cached processor is separated from the memory components such that the cached processor provides support for the memory components, thereby providing a diffused memory architecture with diffused memory capabilities. The memory components can constitute, for example, memory devices such as diffused memory, matrix memory, R-Cell memory components, and the like, depending on design considerations.

Abstract: A switched preconditioner circuit is provided at the power input end of a light source to effectively drop the voltage of the light source to zero volts whenever the light source is required to be in an OFF state thereby eliminating the problem of unwanted current through the light source. The preconditioner circuit may include a terminal connected to a first power potential, a terminal connected to a power node at the power input end of the light source, and an input to receive a preconditioner control signal to place the preconditioner circuit in one of an ON state and an OFF state. The preconditioner circuit supplies the voltage to the power node in its ON state and effectively eliminates the voltage to the power node in its OFF state.

Abstract: A method and apparatus for decoding and de-interleaving a received encoded and interleaved signal, the method employing and the apparatus including a single decoder coupled to a common buffer, the common buffer size equal to a frame of the received signal and the method further employing, and the apparatus further including, an address controller that causes data to be de-interleaved when read from the buffer and data to be interleaved when written to the buffer.

Abstract: A method of fabricating integrated circuits according to a first design. One first pattern is common with a second design, and one second pattern is unique to the first design. The first pattern is imaged using a first mask having first patterns formed in a block thereon. No other patterns of the first and second designs are formed on the first mask. The second patterns are imaged on the substrate using a second mask having second patterns formed in a block thereon. At least one third layer pattern is formed on the second mask.

Abstract: Embodiments of the invention include a method, apparatus and system for providing a Serial Attached SCSI (SAS) domain management application using a domain overlay architecture. The method includes comparing user constructs or data sets defining an existing domain overlay with device data that identifies various network devices in at least one SAS domain, and binding the existing domain overlay to an SAS domain if the existing domain overlay and the SAS domain are uniquely associated with one another. The method also includes creating a new domain overlay that is uniquely associated with an SAS domain for any SAS domain that is not bound to an existing domain overlay. A domain overlay and an SAS domain are not uniquely associated with one another unless the domain overlay references only network devices within the SAS domain and the network devices within the SAS domain are referenced only by the domain overlay.

Abstract: A method of evaluating the feasibility of a CoreSight trace architecture in a SoC before the hardware and/or firmware is available allowing for better die size estimates (IO count and gate count) and package requirement for the design in the early stages of planning.

Abstract: The present invention is directed to an optical disc recorder laser power control apparatus utilizing two different current sources to solve the problem caused by the contradiction between control resolution and control range. The first current source and the second current source are connected in parallel to a single control output pin. The first current source and the second current source may work independently from each other. The laser driver controls emission power of one of the laser diodes with a driving current supplied from the single control output pin coupled to both the first current source and the second current source. Advantageously, the fine laser power control pitch from the first current source contributes to fine control resolution, while the coarse laser power control from the second current source provides a wide control range for various kinds of laser diodes.

Abstract: Methods and systems for customizing information in a memory associated with a SAS host bus adapter (“HBA”). A SAS HBA typically includes a memory component that stores information common to all SAS HBA's manufactured by a particular vendor (e.g., common instructions and data). In addition, each HBA memory component typically includes some information unique to each HBA (e.g., board trace number, SAS address, configuration page, boot record, etc.). Features and aspects hereof permit pre-programmed memory components to be integrated with a SAS HBA to eliminate a step to program an assembled HBA through a specialized, one-time interaction to add required unique information. Thus a manufacturer may simply integrate a pre-programmed memory component to an otherwise completed HBA assembly to complete the product manufacturing without need for a special programming step. Or a design or test engineer may simply replace a memory component to change unique information on the HBA.

Abstract: A method for correcting a plurality of violations in a circuit design and new cells used in the method are disclosed. The method generally includes the steps of (A) implementing a first engineering change order in the circuit design to correct a first of the violations, (B) implementing a second engineering change order with a special cell to correct a second of the violations, the special cell having a plurality of interfaces available for a signal path associated with the second violation, each of the interfaces having a characteristic appropriate to correct the second violation, each of the characteristics having a different performance and (C) routing the signal path to one of the interfaces to fix the second violation.

Abstract: A circuit and method are presented for signal processing and routing of digital voice telephony signals, using a specialized high-density integrated circuit voice processor. The voice processor performs several essential functions required for telephony processing, including echo cancellation, protocol conversion, and dynamic range compression/expansion. These functions are traditionally performed by multiple circuits or modules. By combining these capabilities in a single device, power and circuit board area requirements are reduced. The embodiment of the circuit and method disclosed herein include novel implementations of a time-slot interchange circuit and a telephony signaling circuit. Both of these circuits are designed to minimize demands on the signal processing engines incorporated within the voice processor, and account for very little of the on-chip circuitry.

Abstract: A method for obtaining an optimal reflectivity value for complex multilayer stacks is disclosed. Aspects of the present invention include generating a model of a multilayer stack and parameterizing each layer by a thickness and an index of refraction; allowing a user to input values for the parameters; calculating an extrema for a cost function of reflectivity R using the input parameter values; calculating sensitivity values S for the extrema points; and obtaining an optimal value by calculating a cost function R+S.

Abstract: An apparatus comprising a focus controller, a photo-diode sensor, a data circuit, a focus error creation circuit and a focus offset circuit. The focus controller may be configured to control a lens in relation to a laser beam and allow the laser beam to focus on a disc. The photo-diode sensor may be configured to generate one or more photo-diode signals in response to the laser beam. The data circuit may be configured to generate one or more disc status signals in response to the one or more photo-diode signals. The focus error creation circuit may generate a focus error signal. The focus error signal may provide a first value based on a focus point of the laser beam. The focus offset circuit may be configured to offset the first value of the focus error signal to a second value in response to the disc status signals to allow the focus controller to move the lens to a position which will increase the focus point of the laser beam on the disc.

Abstract: A method and apparatus which provides that, in a voice over network, incoming packets are analyzed and the appropriate moment to increase or decrease the nominal delay associated with a jitter buffer is determined. Hence, the nominal delay is adjusted at an appropriate moment based on network jitter characteristics. Preferably, the nominal delay is adjusted when voice activity is absent. The method and apparatus provide for improved play out of the jitter buffer, and provide improved performance.

Abstract: An apparatus comprising (i) a segmentor circuit, (ii) a plurality of encoders and (iii) a multiplexer circuit. The segmentor circuit may be configured to segment a picture into a plurality of strips. Each of the plurality of encoders may be configured (i) to encode respective strips of the plurality of strips in parallel and (ii) to transfer context information with at least one other encoder of the plurality of encoders. The multiplexer circuit may be configured to combine the encoded strips from the plurality of encoders into an encoded bit stream.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an MPEG packet data stream. The second circuit may be configured to (i) scramble the data stream to generate a scrambled data stream, (ii) encode the scrambled data stream to generate an encoded data stream, (iii) interleave the encoded data stream, (iv) encode the interleaved data stream, (v) modulate the encoded data stream, and (vi) filter the modulated data stream.

Abstract: Exemplary techniques for turning off the clock signal to flip flops are described, which may reduce power consumption by electronic devices. In an implementation, a clock-gating logic turns off the clock signal to a flip flop when a data input of the flip flop remains untoggled. The reduction in power consumption is envisioned to also reduce heat generation.

Abstract: A technique to enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.

Abstract: A fast active DCAP cell which has a short turn-on time, achieves a high capacitance density, and which minimizes leakage overhead during its normal operation mode is disclosed. The DCAP cell has a pair of PMOS transistors that have their drains connected to a gate of a PMOS transistor and their sources connected to the VDD rail. The drain and source of the PMOS transistor are connected to the VSS rail. Likewise, the DCAP cell has a pair of NMOS transistors that have their drains connected to a gate of an PMOS transistor and their sources connected to the VSS rail. The drain and source of the PMOS transistor are connected to the VDD rail. None of the gates of the transistors is connected to the VDD or VSS rail. This protects the gate oxide from being damaged by ESD surge currents.