Abstract: A method for determining when all data has been sent for a given PCI Express bus command issued by a backend entity of a PCI Express bus device, by setting a PCI Express bus packet header tag field of a PCI Express bus packet to indicate a backend entity that originated the PCI Express bus command and whether the PCI Express bus packet is a last packet of the PCI Express bus command, and then inspecting the PCI Express bus packet header tag field of the PCI Express bus packet to determine whether the PCI Express bus packet is the last packet of the PCI Express bus command.

Abstract: A method of testing a tristate element by applying a given value to the tristate, applying an opposite value to a keeper element connected at an output of the tristate, capturing a first value at a downstream position of the tristate, evaluating a second value at the output of the tristate using the first value, comparing the second value to the opposite value, and producing a failure code for the tristate when the second value is not equal to the opposite value. Then, applying the opposite value to the tristate, applying the given value to the keeper element, capturing the first value, evaluating the second value using the first value, comparing the second value to the given value, and producing a failure code for the tristate when the second value is not equal to the given value. A passing code for the tristate is produced when a failure code has not been produced.

Abstract: A RAID level migration system and method are provided that enable RAID level migration to be performed without the use of a hardware RAID controller with NVRAM for storing the migration parameters. Eliminating the need for a hardware controller having NVRAM significantly reduces the costs associated with performing RAID level migration. The system and method are capable of migrating from any arbitrary RAID level to any other arbitrary RAID level.

Abstract: The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure. Aspects of the invention also include methods for forming the dielectric copper barrier layers and associate copper interconnects to the underlying copper lines.

Abstract: An apparatus comprising a first processing circuit and a second processing circuit. The first processing circuit may be configured to generate a plurality of reconstructed samples in response to one or more macroblocks of an input signal. The second processing circuit may be configured to determine a best intra prediction chroma mode 0 predictor for reach chroma sub-block of a current macroblock in response to available reconstructed samples adjacent to the current macroblock.

Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the ground plane used to ground the low speed circuitry of the package.

Abstract: Disclosed is a system that generates a write count value for indicating whether data can be read from a FIFO and a system that generates a read count value for indicating whether data can be written to a FIFO. Each of these systems operates in two separate clock domains. In the system that generates a write count value, write strobes are stored in parallel in a register in a first clock domain. The plurality of synchronizers trigger on a rising edge of the write strobe that is stored in the parallel register and generate an increment pulse in a second clock domain. An up/down counter reads the increment pulse in parallel and increments the up/down counter in parallel. A decrement signal from a read strobe decrements the up/down counter. The output of the counter is fed to a register that provides a write counter value to handshake logic that indicates whether data can be read from a FIFO without underflowing the FIFO.

Abstract: A method for transcoding between videostreams using different entropy coding, comprising the steps of (A) decoding a first videostream using a first set of entropy codes, and (B) generating a second videostream by entropy encoding the decoded first videostream using a second set of entropy codes. The first set of entropy codes and the second set of entropy codes are configured to represent all valid coefficient values of the first videostream.

Abstract: A latch-based integrated circuit random access memory having selectable bit write capability that is less susceptible to disturbing data stored in unselected bits during write operations by utilizing an inhibit signal to block writing of the unselected bits.

Abstract: A rack mount drive blade system having a chassis and a drive blade. The chassis has at least one blade bay to accept a drive blade, where the chassis accepts the drive blade into the blade bay with the drive blade in a horizontal orientation. Each blade bay has chassis to blade electrical contacts including at least one cable having a length, for making electrical connections between the chassis and the drive blade. Each blade bay also has slot portions for engaging the drive blade along a length of the drive blade. The chassis has at least one module bay to accept a shared resource module, where each module bay has chassis to module electrical contacts, for making electrical connections between the chassis and the shared resource module. The drive blade has a printed circuit board for providing electrical connections to and from components on the drive blade.

Abstract: A controller system for detecting and matching link speeds. The present invention provides for a controller system. The controller system is a first controller and a first port. The first port is located in the first controller and has a first link speed. The first controller is adapted to match the first link speed to a second link speed of a second port of a first controlled device that is connectable to the first controller.

Abstract: A system, apparatus and method for testing and measuring high frequency signals on a trace is described. In one embodiment of the invention, a footprint is manufactured on a trace to allow the testing of a signal while reducing the amount of distortion caused by prior art structures and methods. The footprint is designed to reduce stub effects and capacitance on a signal being communicated on the trace.

Abstract: An automated system for validating Peripheral Component Interconnect (PCI) bus adapters or PCI-X bus adapters has a computer, motherboard, a PCI-X bus and isolated test slot for operatively coupling a PCI/PCI adapter under test through the PCI-X bus to the motherboard. The isolated test slot is adapted and arranged to minimize degradation of data flow on the PCI-X bus such that a PCI-X adapter, mounted in the isolated test slot, can negotiate a required operating rate greater than PCI operating rates. It can be configured as a low profile slot in a low profile computer system, such as a 2U low profile system. A method for validating the PCI/PCI-X bus adapters includes operatively coupling the bus adapter under test to the motherboard, negotiating to the required operating rate and testing the functionality of the adapter. The operating rate of the bus adapter can be verified to ensure the PCI/PCI-X bus adapters are tested at required PCI/PC-X rates.

Abstract: A customizable option ROM image that allows a user to modify certain features of a ROM image is described. In one embodiment, a plurality of configuration ROM image modules is provided to a user. These modules may be bundled in a single file along with a software interface application that allows the user to customize one or more of the modules. In particular, the software application provides a simple interface so that a user may identify and change particular ROM image features. Thereafter, a ROM image is built using the modules, some of which may have been modified, so that it may be installed within the customer's system.

Abstract: An improved method and apparatus for controlling the voice channels in sound processors includes: programming a first voice channel to instruct a second voice channel to execute an event when a trigger condition occurs; determining by the first voice channel that the trigger condition has occurred; and instructing the second voice channel to execute the event by the first voice channel. Thus, the need for the CPU to properly time the programmer's desired voice processing events is reduced by having the voice channels themselves be pre-instructed to control another voice channel(s) upon meeting a certain trigger condition. Chains of voice channels are possible and can be as simple or complex as desired. Accurate channel-to-channel event timing is thus possible. Since no interrupts or the polling of status registers is needed, the demands on CPU resources are reduced. System bus bandwidth is also freed for the use of other system components.

Abstract: A system and method increase yield from semiconductor wafer electroplating. The aspects include a semiconductor wafer, the semiconductor wafer comprising a plurality of die areas. A plating ring for holding the semiconductor wafer in position during electroplating is also included, the plating ring substantially surrounding a circumference of the semiconductor wafer and having a width that varies in order to avoid overlap near edge die areas of the semiconductor wafer.

Abstract: Data is cached in a dual-controller storage array having a first cache controlled by a first controller, a second cache controlled by a second controller, and a shared array of persistent storage devices, such as disk drives. When one of the controllers receives a write request, it stores the data in persistent storage, stores a copy of that data in the first cache, and transmits identification data to the second controller that identifies the data written to persistent storage. Using the identification data, the second controller invalidates any data stored in the second cache that corresponds to the data that the first controller wrote to persistent storage. If a controller receives a read request, and the requested data is validly stored in its cache, the controller retrieves it from the cache; otherwise, the controller reads the requested data from persistent storage and caches a copy of the requested data.

Abstract: A comparator receives a first read of voltage differentials from a series of bit cells, compares the first read to a positive voltage offset of a given magnitude, and set bits in a first bit stream to values that are dependent upon whether the voltage differential from a given bit cell is greater than the positive voltage offset. The first bit stream is then stored in a first register. The comparator also receives a second read of the voltage differentials from the series of bit cells, compares the second read to a negative voltage offset of the given magnitude, and sets bits in a second bit stream to values that are dependent upon whether the voltage differential from a given bit cell is greater than the positive voltage offset. The second bit stream is stored in a second register. The comparator then compares the first bit stream to the second bit stream, and set bits in a mask string dependent upon whether the bits in a given position of the first bit stream and the second bit stream are identical.

Abstract: A clock pulse controller includes a test clock pulse input for receiving test clock pulses. A scan enable input receives a scan enable signal having a first state and a second state. A trigger pulse input receives a trigger pulse. A clock pulse output generates a launch clock pulse and a capture clock pulse from the test clock pulses immediately after receiving a predetermined number of the test clock pulses immediately following the trigger pulse. A delayed scan enable output generates a delayed scan enable signal that transitions from the first state to the second state between a leading edge of the launch clock pulse and a leading edge of the capture clock pulse.

Abstract: A pin-based memory power modeling method using arc-based characterization includes steps as follows. All power arcs of a memory model are identified and characterized. A power arc is selected from the identified and characterized power arcs. Output bus switching power is computed by removing overlapping power using the selected power arc, and a temporary value for various input ramp times and output loads is derived. Output pin power for the selected power arc is calculated using the temporary value and a ratio of a number of output bits switching over an entire bus width. Switching power for the selected power arc is calculated by a power estimation tool based on port activity and an input intrinsic power value.