Abstract: A path monitor, a method of monitoring a path, an integrated circuit and a library of standard logic elements. In one embodiment, the path monitor includes: (1) a delay element having an input couplable to an input of a clocked flip-flop associated with a path to be monitored and configured to provide a predetermined delay and (2) a clocked exclusive OR gate having a clock input, a first input coupled to an output of the delay element, a second input couplable to the output of the clocked flip-flop and an output at which the clocked exclusive OR gate is configured to respond to a clock signal to provide an error signal only when logic levels of the first input and the second input differ.

Abstract: Color-difference signals that become unnecessary after rotation are deleted from a second pixel while saving color-difference signals that become necessary after rotation in the second pixel, to thereby form image data conforming to YUV422 format. The image data is then rotated, and subsequently the color-difference signals saved in the second pixel are returned to the original first pixel, to thereby form image data conforming to YUV422 format.

Abstract: A method and computer program for detecting and locating defects in integrated circuit die from stimulation of statistical outlier signatures includes receiving as input a test value of an electrical parameter measured for each of a plurality of identically designed electrical circuits, identifying one of the identically designed electrical circuits as an outlier for which the test value of the electrical parameter varies from a mean test value of the electrical parameter for the plurality of identically designed electrical circuits by at least a selected difference, monitoring the test value while subjecting a location on the outlier to a stimulus to detect a change in the test value as a function of the location, and generating as output the location for which the change in the test value is detected to identify a defect in the outlier.

Abstract: A circuit which includes an IP cell having a function select input signal line, combinatorial logic having an output connected to the function select input signal line of the IP cell, a configuration register having an output connected to an input of the combinatorial logic, wherein a high/low input signal line is also connected to the combinatorial logic, wherein the circuit provided that the configuration register receives configuration data during a start-up sequence, and configuration data is held by the combinatorial logic as the configuration register powers down during a functional mode.

Abstract: A method, apparatus, and computer instructions for a storage subsystem. This subsystem includes controller devices, storage devices, and a communications network. The communications network connects the controller devices and the storage devices. The communications network also includes a set of diagnostic outputs. The set of diagnostic outputs is configured to output data sent between two devices from the controller devices and the storage devices for monitoring.

Abstract: A method and apparatus are disclosed in a data processing system for dynamically selecting one of multiple different I/O firmware images for booting a particular I/O controller that is included in the data processing system. Multiple different I/O firmware images are provided. A configuration of the I/O controller is determined. One of the I/O firmware images is identified that supports the configuration of the particular I/O controller. The identified I/O firmware image is then dynamically selected for booting said I/O controller.

Abstract: Circuits and associated methods for testing internal operation of an application integrated circuit. Features and aspects hereof add configurable test interrupt circuits to an application circuit design to permit dynamic, configurable interrupt generation from an integrated circuit based on conditions determined from monitoring of internal signals of the application circuit. The internal signals that may be tested and used to generate test interrupts are those not exposed to the external processor interface of the integrated circuit and thus may be configured to interrupt based on any internal state of the application specific functional circuits of the integrated circuit.

Abstract: A method for abating effluent from an etching process in one embodiment includes advancing etch gas product into a passageway of a gas connector in direct fluid communication with a first chamber of an interior void of an apparatus, advancing a gas from a gas source into said passageway of said gas connector at the same time said etch gas product is being advanced into said passageway, and advancing humidified gas from a humidified gas source into a second chamber of said interior void.

Abstract: Power factor correction and driver circuits and stages are described. More particularly, power factor correction circuits are described that utilize an auxiliary inductor winding for power regulation. Driver circuits configured for electrical loads such as series arrangements of light emitting diodes are also described. An exemplary embodiment of a driver circuit can implement a comparator and/or a voltage regulator to allow for improved output current uniformity for high-voltage applications and loads, such as series configurations of LEDs. Embodiments of PFC stages and driver stages can be combined for use as a power supply, and may be configured on a common circuit board. Power factor correction and driver circuits can be combined with one or more lighting elements as a lighting apparatus.

Abstract: A method for controlling a stepper motor in an optical disc system, comprising the steps of (A) measuring a static offset of a center error signal, (B) measuring a maximum value, minimum value and an average value of the center error signal in response to rotating the optical disc, (C) computing one or more upper threshold values and one or more lower threshold values of the center error signal, (D) sampling the center error signal, (E) comparing the center error signal to the one or more upper threshold values and to the one or more lower threshold values and (F) computing a control output to control the stepper motor in response to comparing the center error signal to the one or more upper and lower threshold values.

Abstract: A method for implementing a flexible sampling-rate encoder, comprising the steps of (A) sampling an input signal at a regular time-interval to produce sampled data, (B) generating a pseudo-random bit sequence having a plurality of bits, wherein each bit corresponds to a different sampling time, (C) encoding a first set of the sampled data to generate an encoded stream when any bit in the pseudo-random bit sequence is equal to a first value, wherein each bit in the encoded stream corresponds to one of the sampling times defined in step (B), and (D) determining the different sampling time for each sample in the encoded stream.

Abstract: A configurable buffer arbiter is provided that combines a time-slot based algorithm, a fairness-based algorithm, and a priority-based algorithm to meet the bandwidth and latency requirements of multiple channels needing access to a buffer memory. The channels have different static and dynamic characteristics. The static channel characteristics include aspects such as a required latency for access to the buffer memory, a required bandwidth to the buffer memory, a preferred latency or bandwidth to the buffer memory, the amount of data the channel can burst in each access to the buffer memory, and the ability for the channel to continuously burst its data to the buffer memory with or without any pauses. The dynamic characteristics include aspects such as whether a channel's FIFO is nearing full or empty, or whether one of the static characteristics has suddenly become more critical. Configuration of the arbiter algorithms exists to optimize the arbiter for both the static and dynamic channel characteristics.

Abstract: A DWT unit applies wavelet transform to an input signal to output transform coefficients, and a quantization unit quantizes those transform coefficients with a quantization step size determined according to target image quality. Then, a rate control unit controls the rate of coded data according to information on the quantization step size. Also, an image-quality control unit controls the rate of only part of coded data which is determined from a priority table. This achieves a compression encoder which operates at high speed with minimal operations.

Abstract: A deep n-well is formed beneath the area of an inductor coil. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch of shallow trench isolation is patterned over the n-well. The shallow trench isolation reduces and confines the inductively coupled surface currents to small areas that are then isolated from the rest of the chip.

Abstract: A method for detecting progressive material in a video sequence is disclosed. The method generally includes the steps of (A) calculating a plurality of block statistics for each of a plurality of blocks in a current field of the video sequence, (B) calculating a plurality of field statistics by summing the block statistics over all of the blocks in the current field, (C) calculating a noise level for the current field based on a subset of the block statistics from each of the blocks and (D) generating a mode flag for the current field based on both (i) the field statistics and (ii) the noise level, wherein the mode flag identifies if the current field is part of a 2:2 pull-down pattern.

Abstract: A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design. The highest level design is first produced. Then, in a programmed computing system without user intervention, the highest level design is automatically processed to selectively remove at least one predetermined metal layer. A closest remaining overlying layer to the at least one removed metal layer is automatically mapped to a closest remaining underlying layer to the at least one removed metal layer, thereby producing the at least one lower level design.

Abstract: A packetized data bus interface may be placed in a mode where data packets may be transmitted that are much larger than the standard packet size. The mode may allow the interface device and any other devices, networks, or transmission lines attached to the interface device to be more thoroughly exercised than previously able. The mode may be used for characterizing various aspects of the data interface.

Abstract: A system and method for controlling access to parameter blocks of a sound processor. According to the method and system disclosed herein, the present invention includes a host, a sound processor coupled to the host, and at least two copies of a parameter block associated with the sound data. The sound processor can access a first copy of the at least two copies while the host is accessing a second copy of the at least two copies. As a result, parameter blocks are freely updated by the host processor and freely read by the sound processor without conflict and without performance loss.

Abstract: A method and circuit to control the intensity of lights, illumination fixtures, and displays using pulses of a fixed duration and a fixed frequency (FD/FF) is provided. In particular, the method may be used to control one more light sources. By varying the number of pulses in a control burst, the total current flowing through the light source may be precisely controlled providing greater accuracy than other methods, such as, for example, PWM or variable pulse frequency. The FD/FF technique may be used in conjunction with any number of light sources, and finds particular application in LED displays and for any type of LED illumination fixture.