Abstract: A serializer-deserializer and a method of deserializing data. In one embodiment, the serializer-deserializer includes: (1) an analog-to-digital converter configured to receive a serial data stream and provide a digital output based thereon, (2) a digital comparator coupled to the analog-to-digital converter and configured to compare the digital output to an output table to yield candidate output bits, (3) a digital feedback equalizer coupled to the digital comparator and configured to generate the output table based on the candidate output bits and (4) a multiplexer coupled to the digital comparator and configured to select output bits from among the candidate output bits to form a discrete bit sequence.

Abstract: A method may include providing a management application with firmware information of a RAID controller and/or system information of a particular set of physical disks forming a particular underlying RAID implementation that is relevant to creating a configuration on the RAID controller of the particular underlying RAID implementation to enable the management application to configure the RAID controller of set of physical disks forming any RAID implementation without prior knowledge of firmware information of the RAID controller and system information of at least one of set of physical disks forming a RAID implementation and determining the configuration of the particular underlying RAID implementation using a decision making process of the management application based on of a firmware information of the RAID controller and system information of the particular set of physical disks forming the particular underlying RAID implementation to determine the configuration of the particular underlying RAID implementat

Abstract: Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a pipelined analog to digital converter is disclosed that includes two or more comparators. A first of the comparators is operable to compare an analog input to a first voltage reference upon assertion of the first clock, and a second of the comparators is operable to compare the analog input to a second voltage reference upon assertion of the second clock. The pipelined analog to digital converters further include a multiplexer tree with at least a first tier multiplexer and a second tier multiplexer. The first tier multiplexer receives an output of the first comparator and an output of the second comparator, and the second tier multiplexer receives an output derived from the first tier multiplexer. The second tier multiplexer provides an output bit.

Abstract: Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, an analog to digital converter is disclosed that includes an analog input that is provided to a comparator bank. The comparator bank receives a reference indicator, and is operable to provide a current output based at least in part on a comparison of the analog input with a reference threshold corresponding to the reference indicator. The analog to digital converter further includes a range selection filter that is operable to receive the current output and to generate the reference indicator based at least in part on a prior output of the comparator bank.

Abstract: A system and method of reliable and efficient data transfer over serial port are disclosed. In one embodiment, a method of communicating data to a headless system over a communications medium includes transmitting data over the communications medium, ceasing transmitting data over communications medium in response to detecting a change in a status of a pin (e.g., a pin of a Modem Status Register, a Clear to Send, a 5th bit of the Modem Status Register, etc.) on the communications medium, and repeating the transmitting data over the communications medium in response to receiving a request to resend the data. The method may include transmitting a size of the data (e.g., a 2 byte value) over the serial port.

Abstract: A method for automatically detecting a plurality of parameters for a NAND-Flash memory. A first step of the method may include generating a plurality of address cycles for the NAND-Flash memory. A second step may set an address number parameter of the parameters based on (i) a first number of the address cycles generated and (ii) a status signal generated by the NAND-Flash memory responsive to the address cycles. A third step generally includes generating at least one read cycle for the NAND-Flash memory after determining the address number parameter. A fourth step may set a page size parameter of the parameters based on (i) a second number of the read cycles generated and (ii) the status signal further responsive to the read cycles.

Abstract: A method and system of frequency domain equalization. In an embodiment, the frequency domain equalizer system includes a transmit driver. A receiver decision circuit is communicatively coupled to the transmit driver. The receiver decision circuit may have an input signal and an output signal. An all-pass filter may be communicatively coupled to the transmit driver and the receiver decision circuit. The all-pass filter having an all-pass input signal which comprises an integration of a summation of the receiver decision circuit input signal and the receiver decision circuit output signal, each signal being acted upon by at least one band-pass filter.

Abstract: Programmable power management using a nanotube structure is disclosed. In one embodiment, a method includes coupling a nanotube structure of an integrated circuit to a conductive surface when a command is processed, and enabling a group of transistors of the integrated circuit based on the coupling the nanotube structure to the conductive surface. A current may be applied to the nanotube structure to couple the nanotube structure to the conductive surface. The nanotube structure may be formed from a material chosen from one or more of a polymer, carbon, and a composite material. The group of transistors may be enabled during an activation sequence of the integrated circuit. In addition, one or more transistors of the group of transistors may be disengaged from the one or more power sources (e.g., to minimize leakage) when the nanotube structure is decoupled from the conductive surface.

Abstract: An integrated circuit is provided that includes an execution engine and a memory controller. The execution engine is clocked at a first rate and the memory controller is clocked at a second rate that is less than the first rate. Pins on the integrated circuit can transfer data to and from the integrated circuit on both the rising and falling edges of a second clock transitioning at the second clock rate. The integrated circuit is preferably packaged using a lead frame and wire bonds extending from pads on the integrated circuit to corresponding leads. The leads are secured to trace conductors on a surface of a printed circuit board. The board contains no more than two conductive layers separated by a dielectric layer.

Abstract: The present invention is directed to methods of fabricating a high-K dielectric films having a high degree of crystallographic alignment at grain boundaries of the film. A disclosed method involves providing a substrate and then depositing a high-K dielectric material assisted with an ion beam to enable the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric films have a high degree of crystallographic alignment at grain boundaries. Another disclosed method involves providing a substrate and then angularly depositing a material onto the substrate in order to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The result is a dielectric film having a high degree of crystallographic alignment at grain boundaries of the film.

Abstract: A method, apparatus, and computer instructions for a storage subsystem. This subsystem includes controller devices, storage devices, and a communications network. The communications network connects the controller devices and the storage devices. The communications network also includes a set of diagnostic outputs. The set of diagnostic outputs is configured to output data sent between two devices from the controller devices and the storage devices for monitoring.

Abstract: A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.

Abstract: Methods and apparatus to enhance performance of Serial Advanced Technology Attachment (SATA) disk drives in Serial-Attached Small Computer System Interface (SAS) domains are described. In one embodiment, a data packets and/or commands communicated in accordance with SAS protocol may be converted into SATA protocol. Other embodiments are also described.

Abstract: An embodiment of the present invention provides a method to utilize data from many different die sizes and products so that highly detailed wafer profiles can be generated that have an improved signal to noise ratio and spatial resolution. Instead of being limited to single die size like normal wafer maps, this method takes advantage of multiple die sizes and their variation in placement on the wafer to increase the information available about the wafer patterns.

Abstract: An apparatus including a photo detector circuit, a first circuit, a second circuit and a third circuit. The photo detector circuit may be configured to generate an RF signal in response to a laser spot on a surface of an optical disc. The first circuit may be configured to generate a first digital signal in response to an AC-coupled version of the RF signal. The second circuit may be configured to generate a second digital signal in response to a DC-coupled version of the RF signal. The third circuit may be configured to generate one or more detect signals in response to the first digital signal and the second digital signal. Each of the one or more detect signals may indicate a respective condition of the surface of the optical disc.

Abstract: Peer-to peer licensing tracking and control is disclosed. In one embodiment, a method may include individually disabling a controller module when a code to activate the controller module is different from a number embedded in the controller module, and automatically disabling the controller module when the number is associated with another controller module communicatively coupled to the controller module. The method may further include a master controller module periodically querying one or more of controller modules communicatively coupled to the master controller module. The querying may identify the number and the feature associated with each of the controller modules to store in a validation module of the master controller module as a database. When the number of the controller module matches with one or more numbers of the controller modules listed in the database, the controller may be deactivated.

Abstract: A settop box system for capturing and controlling live and recorded audio and video content. The system records digital and analog data from video and audio content, such as in a home entertainment center. The system records data from the content as specified and the data may be sequenced into clips that can be searched and indexed. A user may create comparison programs that allow searches of either pre-recorded or incoming content to be performed. In addition, the program allows editing of recorded programs, such as filtering of audio content or overlaying a video program with a different audio background. Multiple audio and video feeds may be handled simultaneously and the program's functions may be executed without viewing of the content being manipulated. The recorded content may also be indexed and even clips of the content may be indexed.

Abstract: Method and system for dividing a data segment of unknown length into first and second halves, for example, for interleaving the first and second halves. Units of the data segment are written into first and second register files. With respect to the first register file, responsive to determining that the last unit of the data segment has been written into the first register file, units of the data segment in the first register file that are not units of the first half of the data segment are removed, wherein the first register file stores the first half of the data segment.

Abstract: A method for contour reduction in a digital picture is disclosed. The method generally includes the steps of (A) buffering a plurality of luma samples in a current line of the digital picture, each of the luma samples having a respective input value, (B) calculating a plurality of horizontal sum-of-signs along the current line, wherein each of the horizontal sum-of-signs comprises a sum of a plurality of amplitude differences between pairs the luma samples from the current line and (C) generating a plurality of output value based on the horizontal sum-of-signs, one of the output values for each one of the luma samples.

Abstract: A scannable flip-flop and method are provided. The flip-flop includes a clock input, a normal data input, a test data input, a normal data output and a scan data output. The flip-flop has a normal operating mode during which the normal data output is enabled and the scan data output disabled and has a scan-shift mode during which the normal data output is disabled and the scan data output is enabled.