Abstract: Methods and associated structure to assure correct order in delivery of SATA frames over a SAS wide port. In one aspect hereof, new connection requests from a SATA device are rejected until prior frames residing in receive buffers of the SAS/SATA controller are properly processed. In another aspect, when a device is already connected to the controller, the SAS/SATA controller may prevent return of a receiver ready primitive in response to a transmitter ready primitive until previously received frames are removed from the receive buffers.

Abstract: A copper interconnect with a Sn coating is formed in a damascene structure by forming a trench in a dielectric layer. The trench is formed by electroplating copper simultaneously with a metal dopant to form a doped copper layer. The top level of the doped copper layer is reduced to form a planarized surface level with the surface of the first dielectric layer. The doped copper is annealed to drive the metal dopants to form a metal dopant capping coating at the planarized top surface of the doped copper layer.

Abstract: A method of testing a tristate element by applying a given value to the tristate, applying an opposite value to a keeper element connected at an output of the tristate, capturing a first value at a downstream position of the tristate, evaluating a second value at the output of the tristate using the first value, comparing the second value to the opposite value, and producing a failure code for the tristate when the second value is not equal to the opposite value. Then, applying the opposite value to the tristate, applying the given value to the keeper element, capturing the first value, evaluating the second value using the first value, comparing the second value to the given value, and producing a failure code for the tristate when the second value is not equal to the given value. A passing code for the tristate is produced when a failure code has not been produced.

Abstract: A method of stabilizing an identification series of bits by iteratively reading the identification series and logical OR'ing the identification series with a mask string after each read of the identification series. This produces a mask string having a first value in all positions of the mask string where bits in the identification series have never changed value during all of the readings of the identification series, representing stable bits, and a second value in all positions of the mask string where bits in the identification series have changed value during at least one of the readings of the identification series, representing unstable bits. The number of the unstable bits in the mask string having the second value is counted, and a method failure code is selectively reported when the number of unstable bits exceeds a maximum allowable number of unstable bits. An identification string is produced from the stable bits, and an identification code is calculated from the identification string.

Abstract: A method for verifying the proper communication of data packets from an initiator device on a PCIe data bus to a target device on the data bus. A target-specific counter on the initiator is synchronized to an initiator-specific counter on the target with the same value. The initiator writes the value of the target-specific counter into the tag field of the packet header, and also writes an identifier of the initiator into the header. Then the initiator sends the packet to the target on the PCIe data bus. Upon receipt of the packet, the target reads the identifier and checks the value against the appropriate initiator-specific counter on the target. When the value is not equal to the initiator-specific counter on the target, then it generates an error message. An additional memory write with specific data is posted from the initiator to the target. A memory read is posted of the additional memory write location from the initiator to the target.

Abstract: Techniques for vaporizing and handling a vaporized metallic element or metallic element salt with a heated inert carrier gas for further processing. The vaporized metallic element or salt is carried by an inert carrier gas heated to the same temperature as the vaporizing temperature to a heated processing chamber. The metal or salt vapor may be ionized (and implanted) or deposited on substrates. Apparatus for accomplishing these techniques, which include carrier gas heating chambers and heated processing chambers are also provided.

Abstract: The present invention is directed to an online product validation solution integrating an online testing module configured to assist a user to create test cases and a remote test automation module configured to execute the created test cases on remote test systems. When a user creates a test plan, complete test coverage for the test plan may be ensured and cross-checked with product specifications stored in the knowledge database. Moreover, seamless integration of the online testing module and the remote test automation module may provide a uniform interface for generating both manual and automated test cases. Test case status is reported within the test plan in synchronicity with test case execution.

Abstract: A leakage power recovery system and method, and a electronic design automation (EDA) tool incorporating either or both of the system and the method. In one embodiment, the timing signoff tool includes: (1) a power recovery module configured to make first conditional replacements of cells in at least one path in a circuit design with lower leakage cells and estimate a delay and a slack of the at least one path based on the first conditional replacement and (2) a speed recovery module associated with the power recovery module and configured to determine whether the first conditional replacements cause a timing violation with respect to the at least one path and make second conditional replacements with higher leakage cells until the timing violation is removed.

Abstract: The present invention is directed to an apparatus for reducing and constraining EMI (electronic magnetic radiation) emissions without affecting the internals of data storage system components. A baffle is attached to the exterior of the housing of a data storage system component by baffle mounts. The baffle is operable between a closed position, where the baffle blocks EMI emitted by connectors on the data storage system component, and an open position, where the connectors are not blocked allowing for servicing and cable management. The baffle may comprise an EMI absorbing material and be tuned to meet specific EMI requirements. The baffle mounts offsets the baffle from the data storage system component and the baffle includes a number of holes to allow airflow. The adjustable EMI baffling apparatus does not interfere with other mounted components while the data storage system component is mounted in a cabinet.

Abstract: An improved method and apparatus for transmitting digital signals in a communications channel by compensating for distortions due to attenuation of high frequency components suffered by the digital signals. In a preferred embodiment, the digital signals are pulses and the compensation is performed at the transmitter without the need for an emphasis driver, by widening the pulses to compensate for the distortion in the channel that results in narrowing of the pulses incurred in the channel. The resulting pulse train is pre-compensated for the distortions caused by the communications channel. The amount of pre-compensation can be determined statically or dynamically.

Abstract: A method and apparatus are provided for generating and using timing constraints templates for IP cores that can be instantiated in an integrated circuit design. The templates include a plurality of timing constraint statements for inputs and outputs of the respective IP core. At least one of the statements includes a configurable variable, wherein the timing constraints template is configurable through the variable for each of a plurality of instances of the IP core in the integrated circuit design.

Abstract: Methods and apparatus are provided for a fast unbalanced pipeline architecture. A disclosed pipeline buffer comprises a plurality of memory registers connected in series, each of the plurality of memory registers, such as flip-flops, having an enable input and a clock input; and a controlling memory register having an output that drives the enable inputs of the plurality of memory registers, whereby a predefined binary value on an input of the controlling memory register shifts values of the plurality of memory registers on a next clock cycle. A plurality of the disclosed pipeline buffets can be configured in a multiple stage configuration. At least one of the plurality of memory registers can comprise a locking memory register that synchronizes the pipeline buffer. The pipeline buffer can optionally include a delay gate to delay a clock signal and an inverter to invert the delayed clock signal.

Abstract: Disclosed is a method of improving a synthesized circuit design comprising searching the synthesized circuit design for a first instance of a first pattern of gates. The first instance is removed from the synthesized circuit design. The first instance is replaced with a non-synthesized cell. A method of altering a multiplexer implementation comprises receiving a netlist that describes a synthesized logic circuit design. Parsing the netlist to detect a first instance of a first pattern of gates that implements a first multiplexer. The first instance is replaced in the netlist with a technology implementation of the first multiplexer.

Abstract: In one embodiment, an LDPC decoder has one or more reconfigurable adders that generate variable-node messages and one or more reconfigurable check-node units (CNUs) that generate check-node messages. The LDPC decoder has a five-bit precision mode in which the reconfigurable adders and CNUs are configured to process five-bit variable-node and check-node messages, respectively. If the LDPC decoder is unable to properly decode codewords in five-bit precision mode, then the decoder can be reconfigured in real time into a ten-bit precision mode in which the reconfigurable adders and CNUs are configured to process ten-bit variable-node and check-node messages, respectively. By increasing the size of the variable-node and check-node messages from five bits to ten bits, the probability that the LDPC decoder will decode the codeword correctly may be increased.

Abstract: In one embodiment, an LDPC decoder has a plurality of check-node units (CNUs) and a controller. Initially, the CNUs generate check-node messages based on an initial offset value selected by the controller. If the decoder converges on a trapping set, then the controller selects new offset values for missatisfied check nodes (MSCs), the locations of which are approximated, and/or unsatisfied check nodes (USCs). In particular, offset values are selected such that (i) the messages corresponding to the MSCs are decreased relative to the messages that would be generated using the initial offset value and/or (ii) the messages corresponding to the USCs are increased relative to the messages that would be generated using the initial offset value. Decoding is then continued for a specified number of iterations to break the trapping set. In other embodiments, the controller selects scaling factors rather than, or in addition to, offset values.

Abstract: In one embodiment, an LDPC decoder has a controller and one or more check-node units (CNUs). Each CNU is selectively configurable to operate in (i) a first mode that updates check-node (i.e., R) messages without averaging and (ii) a second mode that that updates R messages using averaging. Initially, each CNU is configured in the first mode to generate non-averaged R messages, and the decoder attempts to recover an LDPC-encoded codeword using the non-averaged R messages. If the decoder is unable to recover the correct codeword, then (i) the controller selects the averaging mode, (ii) each CNU is configured to operate in the second mode to generate averaged R messages, and (iii) the decoder attempts to recover the correct codeword using the averaged R messages. Averaging the R messages may slow down the propagation of erroneous messages that lead the decoder to convergence on trapping sets.

Abstract: Embodiments of the present invention are methods for breaking one or more trapping sets in a near codeword of a failed graph-based decoder, e.g., an LDPC decoder. The methods determine, from among all bit nodes associated with one or more unsatisfied check nodes in the near codeword, which bit nodes, i.e., the suspicious bit nodes or SBNs, are most likely to be erroneous bit nodes. The methods then perform a trial in which the values of one or more SBNs are altered and decoding is re-performed. If the trial does not converge on the decoded correct codeword (DCCW), then other trials are performed until either (i) the decoder converges on the DCCW or (ii) all permitted combinations of SBNs are exhausted. The starting state of a particular trial, and the set of SBNs available to that trial may change depending on the results of previous trials.

Abstract: In one embodiment, a reconfigurable cyclic shifter is selectively configurable to operate in (i) five-bit mode to cyclically shift N five-bit messages by up to N degrees or (ii) ten-bit mode to cyclically shift N ten-bit messages by up to N degrees. The reconfigurable cyclic shifter has two five-bit N/2-way non-reconfigurable cyclic shifters. The two non-reconfigurable cyclic shifters together, without additional hardware, do not perform N degrees of cyclic shifting. Thus, five-bit and ten-bit reordering hardware is provided that enables the reconfigurable cyclic shifter to perform up to N degrees of cyclic shifting in the five- and ten-bit modes, respectively. In the five-bit mode, the N five-bit messages are shifted concurrently, where each non-reconfigurable cyclic shifter shifts N/2 of the N messages. In ten-bit mode, N/2 of the N ten-bit messages are shifted concurrently, where each non-reconfigurable cyclic shifter shifts five of the ten bits of each ten-bit message.

Abstract: In one embodiment, a reconfigurable minimum operator has two five-bit non-reconfigurable minimum operators and is selectively configurable to operate in a five- or ten-bit mode. In five-bit mode, the first non-reconfigurable minimum operator determines whether a first five-bit message is less than a second five-bit message, and the second non-reconfigurable minimum operator determines whether a third five-bit message is less than a fourth five-bit message. In ten-bit mode, the first non-reconfigurable minimum operator determines whether a first half of a first ten-bit message is less than a first half of a second ten-bit message, and the second non-reconfigurable minimum operator determines whether a second half of the first ten-bit message is less than a second half of the second ten-bit message. The reconfigurable minimum operator determines whether the first ten-bit message is less than the second ten-bit message based on the comparisons of the first and second non-reconfigurable minimum operators.