Abstract: A storage area network system having a data storage means for storing computer data, a storage manager routine running on a client, the storage manager routine having functional elements for directing snapshots to be taken of the computer data on the data storage means, and a snapshot ranking manager for determining characteristics of the snapshots, and for selectively deleting given ones of the snapshots based at least in part on the characteristics of the snapshots. The characteristics of the snapshots might include the type of application that uses the data in the logical volume from which the snapshots were taken, or mission critical aspects of the data.

Abstract: In some embodiments, a method for managing embedded devices may include one or more of the following steps: (a) loading an embedded web server module, (b) loading a first webpage when loading a first embedded module, (c) replacing the first webpage with a second webpage when a second embedded module is loaded or when a failure is detected by the first embedded module, (d) loading a boot loader module, (e) interacting with the computer system to correct the failure condition, (f) loading an embedded operating system module, and (g) loading a third webpage when loading a RAID application module.

Abstract: A method of fabricating an interconnection between a region of copper material and a conducting region is disclosed. The method includes a step of forming a region of tin material and a step of forming a region of nickel material. The method also includes a step of melting the tin material to induce formation of a nickel/tin/copper intermetallic composition at an interface between the region of copper material and the conducting region. The region of tin material and the region of nickel material define the interface between the region of copper material and the conducting region.

Abstract: A method of motion compensation for an input block is disclosed. The method generally includes the steps of (A) generating a plurality of tap values in response to a motion vector for the input block, (B) generating an interpolated block by programmable filtering a reference block using the tap values, the interpolated block being spatially offset from the reference block by less than a half-pel separation and (C) generating an output block in response to the input block and the interpolated block.

Abstract: An apparatus comprising a first circuit, a second circuit and a disc. The first circuit may be configured to (i) extract video data as data blocks from an input signal and (ii) perform error correction on the data blocks with a delta syndrome based iterative Reed-Solomon decoding. The second circuit may be configured (i) to decode corrected video data into a video format in a first state, (ii) encode the corrected video data a second state and (iii) share an external memory between the first circuit and the second circuit. The disc may be configured to store encoded video data in the second state.

Abstract: Dynamic discovery of active peer applications and information related thereof in a network is described. In one embodiment of the present invention, the discovery and information related to peer applications is maintained by a plurality of network device peers. This information is supplemented by device or peer application failure information, which is identified through point-to-point communication initiated by a failure to receive a multicast packet from a particular network peer application.

Abstract: Apparatus and methods for enabling multiple, unidirectional, virtual connections between a first SAS device and multiple other SAS devices in a SAS domain. An enhanced first SAS device may be substantially simultaneously coupled to each of two other SAS devices through one or more appropriately enhanced SAS expanders to allow substantially simultaneous unidirectional virtual connections from the first SAS device to both of the second and third SAS devices. Each virtual connection is, in essence, a half-duplex connection such that the first device is transmitting information to a second SAS device substantially simultaneous with the first device receiving information from a third SAS device. The enhancements are provided in a manner to allow backward compatibility with current SAS specifications for connectivity among devices not suitably enhanced in accordance with features and aspects hereof (e.g., with legacy devices).

Abstract: A temperature monitoring circuit for an integrated circuit on a monolithic chip, the temperature monitoring circuit comprising a temperature sensor disposed on the monolithic chip, a system monitor disposed on the monolithic chip, and electrically conductive traces for electrically connecting the temperature sensor to the system monitor. In this manner, the temperature on the monolithic chip can be monitored by the integrated circuit itself, and appropriate action can be programmed to occur upon attaining various set points or conditions.

Abstract: Disclosed is a flipchip scheme where power and ground bumps are arranged in a striped configuration. Specifically, there are a plurality of lines of power bumps, and a plurality of lines of ground bumps. Each line of power bumps is interconnected by a mesh core power bus, and each line of ground bumps is interconnected by a mesh core ground bus. The busses are shorted across the bumps without having to use metal tab extensions. This arrangement provides that: signal routing can be provided between the lines of bumps; and/or the mesh core power busses can be provided as being wider in order to provide improved power mesh performance and/or in order to reduce or eliminate the metal required on the second top-most metal layer.

Abstract: A device for soft decoding contains a set of operational elements, each being capable of performing one of several different functions. The operational elements may be dynamically configured with input and output connections to registers, memory locations, and other operational elements to perform various steps in a soft decoding scheme. In many cases, the operational elements may be configured to operate in a pipeline mode where many sequences of operations may be performed in parallel. Some embodiments may be reconfigured at each clock cycle to perform different steps during a decoding operation. The device may be used to perform several different soft decoding schemes with the flexibility of a programmable processor but the throughput of a hardware implementation.

Abstract: A FIFO memory having an available capacity of no more than N words deep by M bits wide. A write port receives data to store in the FIFO memory, and a read port provides the data stored in the FIFO memory. X memories store the data, where each of the X memories has a size of N/X by M. Control logic receives the data from the write port, writes the data into at least one of the X memories in a serial write manner, reads the data from at least one of the X memories in a serial read manner, and provides the data to the read port. The control logic also disables power to selected ones of the X memories when they are not being written to or read from. The FIFO memory is configured to both read and write the data at a given time to a given one of the X memories.

Abstract: Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.

Abstract: A system and method for removing one volume of a redundant data storage system, keeping a delta log of subsequent changes to the remaining volumes of the redundant data storage system, replacing the volume, and rebuilding the volume by using the delta log is disclosed. The system and method are applicable to redundant data storage systems such as RAID systems and mirrored backup systems including remote mirrored systems.

Abstract: The present invention is directed to a Fiber Selective Control Switch system for simulating human intervention during a test process for fiber network environments. The Fiber Selective Control Switch system may comprise a MCU, and at least one FSCS module mounted on a SFP device. The MCU is download programmable with basic code, which remotely controls FSCS modules. Each FSCS module coupled to the MCU may include two MOSFETs and a pull down resistor. A positive signal voltage from the MCU to the FSCS module mounted on SFP device will disconnect the fiber connection. A low signal voltage from the MCU to the FSCS module will re-connect the fiber connection. Advantageously, the FSCS system may not affect normal fiber operations due to fast switching characteristics of MOSFET devices and the MCU's low power requirement.

Abstract: A video encoder is disclosed that includes an encoder circuit, a quantizer circuit and a control circuit. The encoder circuit may be configured to generate a number of coefficient values in response to a video stream and a number of quantized values. The quantizer circuit may be configured to generate the number of quantized values in response to the coefficient values, two or more quantization dead zones and two or more offsets. The control circuit may be configured to set the two or more quantization dead zones and the two or more offsets to different values. The two or more quantization dead zones and the two or more offsets are independently programmable.

Abstract: A process is disclosed for configuring a base platform having ASIC and FPGA modules to perform a plurality of functions. A verified RTL hardware description of a circuit is mapped and annotated to identify memory programmable functions. The memory programmable functions are grouped for assignment to FPGA modules. The non-memory programmable functions are synthesized to ASIC modules, and the memory programmable functions are synthesized to FPGA modules. Placement, signal routing and boundary timing closure are completed and the platform is configured by adding metallization layer(s) to configure the ASIC modules and creating a firmware memory to configure the FPGA modules. An over-provisioning feature in the FPGA modules permits post-fabrication alteration of logic functions.

Abstract: The present invention is directed to a method of fabricating a high-K dielectric films having a high degree of crystallographic alignment at grain boundaries of the film. A disclosed method involves providing a substrate and then depositing a material used in forming the high-K dielectric film and also using an ion beam to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric film having a high degree of crystallographic alignment at grain boundaries of the film. Another disclosed method involves providing a substrate and then angularly depositing a material onto the substrate in order to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric film having a high degree of crystallographic alignment at grain boundaries of the film.

Abstract: A reusable software block is adapted to control multiple instantiations of a peripheral device within a system. A device hardware abstraction layer defines offset values for registers of the peripheral device and a data structure for the peripheral device. A platform hardware abstraction layer defines an address map of the system, and is adapted to initialize each instantiation of the peripheral device via calls to the device hardware abstraction layer.

Abstract: An electronic design automation (EDA) tool for and method of optimizing a placement of process monitors (PMs) in an integrated circuit (IC). In one embodiment, the EDA tool includes: (1) a critical path/cell identifier configured to identify critical paths and critical cells in the IC, (2) a candidate PM position identifier coupled to the critical path/cell identifier and configured to identify a set of candidate positions for the PMs, (3) a cluster generator coupled to the critical path/cell identifier and configured to associate the critical cells to form clusters thereof and (4) a PM placement optimizer coupled to the candidate PM position identifier and the cluster generator and configured to place a PM within each of the clusters by selecting among the candidate positions.

Abstract: An arbitrary function may be represented as an optimized decision tree. The decision tree may be calculated, pruned, and factored to create a highly optimized set of equations, much of which may be represented by simple circuits and little, if any, complex processing. A circuit design system may automate the decision tree generation, optimization, and circuit generation for an arbitrary function. The circuits may be used for processing digital signals, such as soft decoding and other processes, among other uses.