Abstract: In one embodiment, a reconfigurable adder has first and second five-bit non-reconfigurable adders and is selectively configurable to operate in a five-bit mode or a ten-bit mode. In five-bit mode, the first non-reconfigurable adder adds first and second messages to generate a first sum, and the second non-reconfigurable adder adds third and fourth messages to generate a second sum. In ten-bit mode, the first non-reconfigurable adder adds a first half of a first ten-bit message and a first half of a second ten-bit message to generate a first partial sum and a carry-over bit. The second non-reconfigurable adder adds a second half of the first ten-bit message, a second half of the second ten-bit message, and the carry-over bit to generate a second partial sum. A ten-bit sum is then generated by combining the first and second partial sums.

Abstract: In one embodiment, a reconfigurable two's-complement-to-sign-magnitude (2TSM) converter has two five-bit non-reconfigurable 2TSM converters and is selectively configurable to operate in a five-bit mode or a ten-bit mode. In five-bit mode, the first and second non-reconfigurable 2TSM converters concurrently convert first and second five-bit messages, respectively, from two's-complement-to-sign-magnitude format. In the ten-bit mode, the first and second non-reconfigurable 2TSM converters concurrently convert first and second halves of a ten-bit message, respectively, from two's-complement-to-sign-magnitude format. The reconfigurable 2TSM converter then generates a ten-bit sign-magnitude message based on the conversions of the two non-reconfigurable 2TSM and a carry-over bit. In another embodiment, a reconfigurable sign-magnitude-to-two's-complement (SMT2) converter comprises the reconfigurable 2TSM described above.

Abstract: In one embodiment, the present invention determines index values corresponding to bits of a binary vector that have a value of 1. During each clock cycle, a masking technique is applied to M sub-vector index values, where each sub-vector index value corresponds to a different bit of a sub-vector of the binary vector. The masking technique is applied such that (i) the sub-vector index values that correspond to bits having a value of 0 are zeroed out and (ii) the sub-vector index values that correspond to the bits having a value of 1 are left unchanged. The masked sub-vector index values are sorted, and index values are calculated based on the masked sub-vector index values. The index values generated are then distributed uniformly to a number M of index memories such that the M index memories store substantially the same number of index values.

Abstract: In one embodiment, an LDPC decoder attempts to recover an originally-encoded LDPC codeword based on a set of channel soft-output values. If the decoder observes a trapping set, then the decoder compares the observed trapping set to known trapping sets stored in a trapping-set database to determine whether or not the observed trapping set is a known trapping set. If the observed trapping set is not known, then the decoder selects a most-dominant trapping set from the trapping-set database and identifies the locations of erroneous bit nodes in the selected trapping set. Then, the decoder adjusts the channel soft-output values corresponding to the identified erroneous bit nodes. Adjustment is performed by inverting some or all of the hard-decision bits of the corresponding channel soft-output values and setting the confidence value of each corresponding channel soft-output value to maximum. Decoding is then restarted using the adjusted channel soft-output values.

Abstract: The present invention is directed to an apparatus for reducing and constraining EMI (electronic magnetic radiation) emissions without affecting the internals of data storage system components. A baffle is attached to the exterior of the housing of a data storage system component by baffle mounts. The baffle is operable between a closed position, where the baffle blocks EMI emitted by connectors on the data storage system component, and an open position, where the connectors are not blocked allowing for servicing and cable management. The baffle may comprise an EMI absorbing material and be tuned to meet specific EMI requirements. The baffle mounts offsets the baffle from the data storage system component and the baffle includes a number of holes to allow airflow. The adjustable EMI baffling apparatus does not interfere with other mounted components while the data storage system component is mounted in a cabinet.

Abstract: A layered decoder that uses a non-standard schedule, where a non-standard schedule is a schedule where the frequency of one or more layers in the schedule is greater than one. When the layered decoder converges on a near codeword using an initial schedule, the layered decoder identifies the layer Lmaxb of the near codeword, which layer contains the greatest number of unsatisfied check nodes, and selects a subsequent non-standard schedule from a schedule set. The non-standard schedules in the schedule set are sorted by key layer, where the key layer is a layer that appears in the non-standard schedule with the greatest frequency. The layer decoder selects a non-standard schedule from the schedule set where the key layer of selected non-standard schedule is equal to the identified Lmaxb value.

Abstract: A method for selecting a population of schedules of an n-layer decoder for offline schedule testing. The method identifies one or more triads, where a triad is a sequence of three layers where no layer is repeated. The method selects a set of schedules where each of the identified triads is contained in at least one schedule. The method associates each selected schedule with one or more key-layer values, where a key layer is the middle layer of a triad contained within the schedule.

Abstract: A decoder-implemented method for layered decoding that, when the decoder converges on a near codeword using an initial schedule, (i) selects a subsequent schedule from a schedule set based on the layer Lmaxb of the near codeword, which layer contains the greatest number of unsatisfied check nodes and (ii) re-performs decoding using the subsequent schedule. When used in an offline schedule-testing system, the layered-decoding method (i) identifies which schedules, out of a population of schedules, correctly decode a decoder input codeword and (ii) associates the identified schedules with the Lmaxb value of the near codeword.

Abstract: Embodiments of the invention include a method for modifying firmware settings within a data storage controller, such as a data storage controller used in a Redundant Array of Inexpensive Disks (RAID) storage array. The method includes extracting a sub-module from a firmware image stored in the controller, stripping off the sub-module's header, decompressing the remaining compressed image by replacing the stripped sub-module header and an extended image header in the compressed image with an extended header image that allows conventional decompression, and separating the decompressed image into its executable code and at least one settings group.

Abstract: In one embodiment, a turbo equalizer has a channel detector that receives equalized samples and generates channel soft-output values. An LDPC decoder attempts to decode the channel soft-output values to recover an LDPC-encoded codeword. If the decoder converges on a trapping set, then an adjustment block selects one or more of the equalized samples based on one or more specified conditions and adjusts the selected equalized samples. Selection may be performed by identifying the locations of unsatisfied check nodes of the last local decoder iteration and selecting the equalized samples that correspond to bit nodes of the LDPC-encoded codeword that are connected to the unsatisfied check nodes. Adjustment of the equalized samples may be performed using any combination of scaling, offsetting, and saturation. Channel detection is then performed using the adjusted equalized samples to generate an updated set of channel soft-output values, which are subsequently decoded by the decoder.

Abstract: The present invention is directed to a customizable development and demonstration platform for structured ASICs. In an exemplary aspect of the present invention, the present platform may include a structured ASIC which is built on a slice and which may be flexible enough for a number of possible application developments. This flexibility may be achieved by incorporating a programmable processor in the structured ASIC and by defining interfaces and the use of an external FPGA in the present platform. The structured ASIC may include a complete ARM processor subsystem and a plurality of high speed SERDES ports. The processor subsystem may include a bus interface to the external FPGA, allowing custom gate development and test in the FPGA, prior to incorporating it into the customer product. Through the SERDES ports, the test block may be used to show the electrical characteristics of the SERDES IP. In addition, some SERDES ports may be driven from a link layer realized in the FPGA.

Abstract: A method for transcoding between video streams using different entropy coding, comprising the steps of (A) decoding a first video stream using a first set of entropy codes, and (B) generating a second video stream by entropy encoding the decoded first video stream using a second set of entropy codes. The first set of entropy codes and the second set of entropy codes are configured to represent all valid coefficient values of the first video stream.

Abstract: A FIFO memory having an available capacity of no more than N words deep by M bits wide. A write port receives data to store in the FIFO memory, and a read port provides the data stored in the FIFO memory. X memories store the data, where each of the X memories has a size of N/X by M. Control logic receives the data from the write port, writes the data into at least one of the X memories in a serial write manner, reads the data from at least one of the X memories in a serial read manner, and provides the data to the read port. The control logic also disables power to selected ones of the X memories when they are not being written to or read from. The FIFO memory is configured to both read and write the data at a given time to a given one of the X memories.

Abstract: A method of determining whether voltage from an aggressor net exceeds a voltage threshold on a victim net design in an integrated circuit design. Probabilistic noise from the aggressor net on the victim net is calculated. The probabilistic noise is checked against the voltage threshold, and the victim net design is passed when the probabilistic noise does not exceed the voltage threshold. When the probabilistic noise does exceed the threshold, then an effective noise at a desired mean time to failure is computed, and the effective noise is checked against the voltage threshold. The victim net design is passed when the effective noise does not exceed the voltage threshold, and failed when the effective noise does exceed the threshold.

Abstract: A method for decoding a digital video bit-stream comprising the steps of (A) receiving the digital video bit-stream having (i) a first portion containing image information and (ii) a second portion containing overscan information and (B) extracting the overscan information from the video bit-stream. The overscan information describes a shape of a overscan region absent from the digital video bit-stream.

Abstract: An apparatus comprising a comparator circuit, a reference circuit, a plurality of elements and a logic circuit. The comparator circuit may be configured to generate a difference signal in response to (i) a reference signal and (ii) a test signal. The reference circuit configured to generate the reference signal in response to a first control signal. The plurality of elements may each be configured to generate an intermediate test signal. One of the intermediate test signals may be presented as the test signal by activating one of the test elements, in response to a second control signal. The logic circuit may be configured to generate (i) the first control signal and (ii) the second control signal, each in response to the difference signal.

Abstract: A method for deinterlacing a picture is disclosed. The method generally includes the steps of (A) calculating a potential sample at a location interfaced with a first field of the picture by temporal filtering, (B) evaluating a protection condition in a current region around the location after inclusion of the potential sample and (C) calculating an interpolated sample at the location by vertical spatial filtering the first field in response to the protection condition indicating a significant increase in a vertical activity within the current region due to the potential sample.

Abstract: A variable node processing unit with N+1 inputs, having at least a first bank of two-input adders and a separate last bank of two-input adders, where the banks of adders are disposed in series.

Abstract: A process is disclosed for configuring a base platform having ASIC and FPGA modules to perform a plurality of functions. A verified RTL hardware description of a circuit is mapped and annotated to identify memory programmable functions. The memory programmable functions are grouped for assignment to FPGA modules. The non-memory programmable functions are synthesized to ASIC modules, and the memory programmable functions are synthesized to FPGA modules. Placement, signal routing and boundary timing closure are completed and the platform is configured by adding metallization layer(s) to configure the ASIC modules and creating a firmware memory to configure the FPGA modules. An over-provisioning feature in the FPGA modules permits post-fabrication alteration of logic functions.