Abstract: A method for reducing variation in a desired property between transistors in an integrated circuit that is fabricated with a given process. The process is characterized to form a mathematical model that associates changes in polysilicon density and active density in the integrate circuit with changes in gate length and gate width in the transistors, and associates changes in the gate length and the gate width to the desired property. The integrated circuit is laid out with space sufficient to adjust the gate length and the gate width of the transistors without violating design rules of the transistors. The integrated circuit is divided into portions, and for at least a given one of the portions of the integrated circuit, the polysilicon density and the active density of the given portion is measured.

Abstract: Locations of IC tags affixed to items are automatically recognized without requiring interrogators or antennas are allocated at respective inventory locations. To attain this object, interrogator 1 firstly transmits a unique ID readout command specifying read range, and corresponding IC tags 2a, 2b, 2c sequentially reply their unique IDs (Xa), (Xb), (Xc) respectively. At the same time, interrogator 1 transmits a probe signal send out command specifying ID, and corresponding IC tags 2a, 2b, 2c sequentially send out probe signals respectively. IC tag 2 that detects a probe signal with reception strength more than a predetermined level stores in its memory IDs (Xa), (Xb), (Xc) that interrogator 1 specified as adjacent ID. Then, interrogator 1 transmits an adjacent ID readout command specifying ID, and corresponding IC tags 2a, 2b, 2c sequentially reply adjacent IDs (Xb), (Xa.Xc), (Xb) stored in their memory respectively.

Abstract: Circuits and systems including a startup circuit coupled to a reference source for providing startup current to the reference source wherein no transistor of the startup circuit experiences a stress condition and wherein the startup circuit consumes no static current following stabilized, steady-state operation of the reference source.

Abstract: A method for analyzing a circuit design in preparation for a simulation. The method generally includes the steps of (A) marking each of a plurality of modules between a target module of the modules and a top module of the modules in a hierarchy of the circuit design as a first type by traversing upward through the hierarchy starting from the target module, (B) marking each of the modules as a second type where a parent module of the modules is marked as the first type by traversing downward through the hierarchy starting from the top module and (C) marking each of the modules as a third type where the parent module is not marked as the keep type by traversing downward through the hierarchy starting from the top module.

Abstract: A method for glitch-free updates of a standard cell-based programmable delay including the steps of (A) generating an output signal in response to an input signal and a plurality of first control signals and (B) generating the plurality of first control signals in response to the output signal and a plurality of second control signals. The output signal may include a delayed version of the input signal. An amount of delay between the input signal and the output signal may be determined based upon the plurality of first control signals.

Abstract: An apparatus and method are disclosed for testing a hard macro that is embedded in a system on a chip (SOC) that is included in an integrated circuit chip. The SOC includes the hard macro. A logic design and operation of the hard macro are unknown. A test wrapper is embedded in the SOC. The test wrapper includes a scan chain. The test wrapper surrounds inputs and outputs of the hard macro. The test wrapper receives a known test data pattern in the scan chain that is included in the test wrapper. The hard macro receives from the test wrapper a set of non-test standard SOC inputs when the SOC is not in a test mode and receives the known test data pattern when the SOC is in the test mode. The hard macro generates a set of outputs in response to the inputs. The hard macro is tested utilizing the known test data pattern.

Abstract: A blade-system computer component with a chassis and a blade. The chassis has a housing for a blade, chassis electrical contacts for making electrical connections to the blade, and two rails for engaging the blade along two sides of a length of the blade. Each of the two rails has a slider portion and a rack portion that both engage the blade, and are both disposed along an entire length of the two rails. The blade has blade electrical contacts for making electrical connections to the chassis, two glides disposed along the entire length of the two sides of the blade, where each of the two glides engage the slider portion of each of the two rails, and provide stability to the blade during relative movement between the blade and the chassis. At least one pinion engages the rack portion of at least one of the two rails, and provides dampening to the relative movement between the blade and the chassis.

Abstract: The present invention is directed to structures and methods of fabricating nanotube electromechanical memory cells having a bottom electrode with a substantially planar contact surface. The bottom electrode is configured so that during the operation of the memory cell the nanotube crossbar of the cell can make contact with a substantially planar surface of the bottom electrode.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a control signal in response to a measurement of inter-picture motion between a current picture and a first reference picture. The second circuit may be configured to select the first reference picture or a second reference picture as a better reference picture for motion estimation in response to the control signal.

Abstract: A ROM-based multiple match system and method for producing a match signal in an addressable memory system are described. In various embodiments of the present invention, a ROM is used to generate single match and multiple match signals, as well as encoded address signals indicating a matching location(s) within the memory. The ROM is provided with specific entries in the form of a lookup table, which are used to signal combinational logic that provides an output to the system. In certain embodiments of the invention, the ROM may be divided into hierarchical sub-blocks that provide more efficient processing of a digital data related to matching of an input word, improved usage of space within a chip or better scalability across the multiple match system.

Abstract: A circuit for providing a bit string, the circuit including a plurality of commonly wired, substantially identical bit cells in a string, where each bit cell is designed to read as only one of a logical high and a logical low upon a given input, and each bit cell comprises a bit in the bit string. An enable line is associated with each of the bit cells, where each enable line has a fuse that is adapted to be activated upon application of a signal by a tester. Each bit cell is configured so as to be logically isolated from all others of the plurality of bit cells in the string when the fuse associated with the bit cell is activated. The circuit is adapted such that bit cells having fuses that are activated are logically removed from the bit string.

Abstract: An arrangement and method for fabricating a semiconductor wafer which utilizes a nonaqueous solvent rinse is disclosed.

Abstract: A method of feed-forward DC restoration in a perpendicular magnetic read channel is disclosed. The method generally includes the steps of (A) generating a feed-forward signal by performing a first detection on an input signal, wherein a DC component of the input signal was previously filtered out in the perpendicular magnetic read channel, (B) generating a restored signal by summing the input signal and the feed-forward signal, the summing restoring the DC component previously filtered out and (C) generating an output signal by performing a second detection on the restored signal, wherein the first detection is independent of the second detection.

Abstract: A packaged integrated circuit having a thermal pathway to exhaust heat from the integrated circuit. The integrated circuit is disposed on a package substrate, with an encapsulant disposed around the integrated circuit. A heat sink is disposed at least partially within the encapsulant, with at least a portion of one surface of the heat sink exposed outside of the encapsulant. The integrated circuit has an uppermost passivation layer, where the passivation layer is not electrically conductive, with a port disposed in the passivation layer. The port extends completely through the passivation layer to expose an underlying layer. A thermal pathway is disposed at least partially within the port, and makes thermal contact to both the underlying layer and the heat sink. The thermal transfer rate of the thermal pathway is greater than the thermal transfer rate either the passivation layer or the encapsulant.

Abstract: A dry/wet bit for controlling dry and wet components of an output sound during processing of an input sound is provided. The bit is configurable by a program to indicate when to reverse the dry and wet components of the output sound. When the bit has a first value, the dry component is calculated by modifying the input sound by an attenuation factor, and the wet component is calculated by providing to a reverberation filter as input the dry component modified by a reverberation factor. When the bit has a second value, the wet component is calculated by providing to the reverberation filter as input the input sound modified by the attenuation factor, and the dry component is calculated by modifying the input to the reverberation filter by the reverberation factor.

Abstract: An apparatus comprising one or more delay circuits, a shimmer detector circuit, an averaging circuit, and a multiplexer. The delay circuits may be configured to have a delay of one or more frame periods based on the format of the input video signal. The shimmer detector circuit may be configured to (i) determine which pixel locations in the input video signal exhibit the YC-interference noise oscillation pattern based on the input signal and the output of the delay circuits and (ii) generate a control signal in response to the output of the delays circuits and the input signal. The averaging circuit may be configured to calculate an average of the input signal and the output of the first delay circuit. The multiplexer may be configured to present (i) the input signal when the control signal is in a first state and (ii) the average signal when the control signal is in a second state.

Abstract: A method and circuit to control the intensity of lights, illumination fixtures, and displays using pulses of a fixed duration and a fixed frequency (FD/FF) is provided. In particular, the method may be used to control one more light sources. By varying the number of pulses in a control burst, the total current flowing through the light source may be precisely controlled providing greater accuracy than other methods, such as, for example, PWM or variable pulse frequency. The FD/FF technique may be used in conjunction with any number of light sources, and finds particular application in LED displays and for any type of LED illumination fixture.

Abstract: A method for generating syndromes for a data block is disclosed. The method generally includes the steps of (A) calculating a plurality of row syndromes and a plurality of column syndromes for the data block arranged as a Reed-Solomon product code, (B) storing only the row syndromes and the column syndromes in a local memory, (C) in an alternating sequence (i)(a) decoding the column syndromes to generate column correction results and (b) updating the row syndromes in response to the column correction results and (ii)(a) decoding the row syndromes to generate row correction results and (b) updating the column syndromes in response to the row correction results.

Abstract: A controller system for detecting and matching link speeds. The present invention provides for a controller system. The controller system is a first controller and a first port. The first port is located in the first controller and has a first link speed. The first controller is adapted to match the first link speed to a second link speed of a second port of a first controlled device that is connectable to the first controller.

Abstract: A method of reading desired data from drives in a RAID1 data storage system, by determining a starting address of the desired data, designating the starting address as a begin read address, designating one of the drives in the data storage system as the current drive, and iteratively repeating the following steps until all of the desired data has been copied to a buffer: (1) reading the desired data from the current drive starting at the begin read address and copying the desired data from the current drive into the buffer until an error is encountered, which error indicates corrupted data, (2) determining an error address of the error, (3) designating the error address as the begin read address, and (4) designating another of the drives in the data storage system as the current drive.