Abstract: The present invention is directed to a method and apparatus for self-configuration of iSCSI storage devices suitable for being utilized as a “plug and play” device for various network environments including direct attached, IP storage area networks with iSNS servers, and IP storage area networks without iSNS servers. The present invention may perform automatic configuration steps including network configuration, storage volume configuration, iSCSI target configuration, iSCSI initiator registration, volume to LUN mapping, and the like. The present invention may be combined with a global configuration setting in the iSCSI storage device to enable automatic configuration. In this manner, the same firmware can be utilized for iSCSI storage devices developed for multiple target markets from direct attached to large IP SANs.

Abstract: A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.

Abstract: A method, system, and a computer program product to provide correct and complete input into a shell generation tool that provides the infrastructure for design and development of an integrated circuit. Given a definition of a platform, in part a partially manufactured semiconductor product having some diffused and some configurable resources, a user can enter data that is correct and complete into the shell generation tool using several techniques. The tool itself can present data for the user to select that is complete and correct, i.e., the data, inter alia, has no syntactic or other errors of an HDL, satisfies the constraints and naming conventions required by the tool, a customer of the semiconductor product, and/or the entity designing the product, provides appropriate timing and voltage levels, and is otherwise compatible with other data in the generation tool.

Abstract: File paths for a plurality of IC design files in a hardware description language are abstracted by parsing description files, or a directory of description file names, to identify file paths to each of the plurality of design files in a first environment. An index is generated correlating each design file and its respective file path. In use, a file path in a second environment of an application is defined for each design file, and the index is applied to the file paths in the second environment to define full file paths for each design file through the first and second environments. The design files are then applied to the application using the full file paths.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to (i) generate a read power signal and (ii) control power of a laser beam emitted from an optical pick-up circuit during a read process. The second circuit may be configured to (i) generate a first write power signal and (ii) control one or more power levels of the laser beam during a write process in response to a second write power signal. The third circuit may be configured to generate the second write power signal and a third write power signal in response to a target write signal.

Abstract: Apparatus and methods for controllably spinning up disk drives in a storage system. A storage system includes a first portion of disk drives that support controllable sequencing of disk drive spin-up and a second portion that do not support controllable sequencing of spin-up. Disk drives in the first portion are configured to be powered on with the storage system and are controllably spun up by issuing appropriate commands to each disk drive. Disk drives in the second portion are configured initially powered off when the storage system is powered on and have power controllably applied thereto to cause spin-up of each disk drive. Disk drives in the first portion may include SAS disk drives and SATA disk drives that support staggered spin-up features. Disk drives in the second portion may include SATA disk drives that do not support staggered spin-up.

Abstract: A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.

Abstract: An apparatus comprising a center error creation circuit, a center error offset injection circuit and a center error controller. The center error creation circuit may be configured to generate a center error signal in response to one or more photo-diode signals. The center error offset injection circuit may be configured to (i) offset the center error signal and (ii) generate an offset signal. The lens controller may be configured to adjust a lens in a sled housing at a mechanical center is response to the offset signal when the apparatus is in a rough seek mode.

Abstract: An arrangement and associated method for abating effluent from an etching process is disclosed.

Abstract: An apparatus comprising a center error creation circuit, a center error controller, and a center error repeatable run out circuit. The center error creation circuit may be configured to generate a center error signal in response to photo-diode signals. The center error controller may be configured to adjust a lens to a center position in a sled housing with a step motor in response to a center error measure signal. The center error repeatable run out circuit may be configured to generate a center error run out signal and the center error measure signal in response to the center error signal. The center error repeatable run out circuit may generate the center error measure signal by measuring the center error signal when the center error run out signal is in a peak phase.

Abstract: An apparatus comprising a drive server, a control server and one or more decoder devices. The drive server may be configured to present one or more DVD data streams in response to one or more input signals. The control server may be configured to present one or more compressed data streams in response to the one or more data streams and one or more request signals. The decoders may be configured to present a decoded video signal and a decoded audio signal in response to one of the compressed data streams and the request signals. The navigation software, which traditionally is processed local to the decoder, may be processed on the control server. The control server may be enabled to control the remote decoder.

Abstract: A computer storage enclosure may comprise a mounting chassis and a computer drive apparatus. The mounting chassis may have a plurality of computer drive guides, a plurality of cam pins, and a mounting chassis disengagement ramp. The computer drive apparatus may include a computer drive, a plurality of shoulder screws, and a computer drive handle. The computer drive apparatus may be mounted on the mounting chassis utilizing the shoulder screws guided by the computer drive guides and secured by the computer drive handle, the cam pins, and the shoulder screws. The computer drive apparatus may include a blade drive and be hot-swappable.

Abstract: A system, apparatus and method for generating and validating extracted timing model files, such as macro library files, are disclosed. A user interface or data template is provided to an engineer that allows for the population of data within particular fields related to timing characteristics of an IP block, cell or core. An extracted timing model file is generated and a validation procedure is performed. This validation procedure may include comparing the information with the file to a test bench have a plurality of test points. In particular, data provided by the engineer is checked against multiple criteria to ensure that this data is valid and/or falls within an appropriate value range constraints. After the validation procedure has completed, the engineer is provided a summary of the validation results.

Abstract: A method for using an identification value for a security application is disclosed. The method may include the steps of (A) generating the identification value based on a plurality of semiconductor fabrication process variations, (B) generating a key by reducing a bit error rate of the identification value, wherein the key may not be available external to the security application and (C) generating an output signal by one of (i) encoding and (ii) decoding an input signal in response to said key.

Abstract: A state machine may have a sequence that is called by multiple threads within the state machine. Prior to calling the sequence, an address specific to the current state is stored in an address register. After the sequence has executed, the address register is queried and the thread may continue. Many different threads may call the sequence. In more complex hardware implemented state machines, the total number of gates may be reduced significantly.

Abstract: A method and system prioritizes frames to be transmitted from a local node to a remote node on a Fibre Channel Arbitration Loop. The frames are placed in context queues. Each kind of context queue is assigned a priority. A determination of a set of transmit frame types is made. A user, an external device, or code may determine the number of transmit frame types in the set. A priority is assigned for each of the transmit frame types in the set. The transmit frame types may be determined by context type. The frames are prepared for transmission. The queues are examined by a suitable method to determine order of transmission. The transmit prioritizer preferably comprises five three-entry deep queues in which the prioritizer places valid contexts classified by transmit frame type. Queued contexts are selected for outgoing frame transmission by a prioritization algorithm aimed at saving the current fibre channel loop tenancy to maximize performance whenever possible.

Abstract: A flow-based FIFO sub-system for a disk formatter in a data processing system that performs data width conversion. The sub-system has a first FIFO unit having a first width interfacing to a first bursting channel, and a second FIFO unit having a second width interfacing to a second bursting channel, the second width not being a multiple of the first width and the first width not being a multiple of the second width. Data width conversion is performed between the first FIFO unit and the second FIFO unit to convert data moving from the first FIFO unit to the second FIFO unit from the first width to the second width, and to convert data moving from the second FIFO unit to the first FIFO unit from the second width to the first width. The sub-system also includes an Error Correcting Code interface between the first FIFO unit and the second FIFO unit for performing in-line correction.