Abstract: The present invention is a method and apparatus in a data processing system that includes a Voice over Internet Protocol (VoIP) communication system for improving transmit and receive data paths. The communication system includes a digital signal processing unit. The digital signal processing unit includes a mandatory coder/decoder (codec) that does not include an internal packet loss concealment (PLC) function, an internal voice activity detection (VAD) function, an internal comfort noise generation (CNG) function, or an internal discontinuous transmission generation (DTX) function. The digital signal processing unit also includes an enhanced codec that includes any combination of the following modules all internal to the enhanced codec: internal packet loss concealment (PLC) function, a voice activity detection (VAD) function, a comfort noise generation (CNG) function, and a discontinuous transmission generation (DTX) function.

Abstract: The present invention is directed to a method of an adaptive procedure table which is capable of providing default behaviors for each procedure if a corresponding procedure is not defined or has been removed from a software build. The default behaviors for each procedure may be defined in a template file provided by a developer before a compile time of software. The present invention may permit a module that defines the implementation of a procedure to be removed from the software build without requiring source code changes. As such, the developer may be allowed to remove or add certain features from a compiled program without introducing compile time or link time errors.

Abstract: A method for identifying memory bit cells and connections for analysis of a circuit block. The method includes defining a bit pattern for each bit cell node in a bit cell. The method also includes defining a node pattern for each node in the circuit block; and matching the node patterns with the bit patterns. The bit cells and corresponding bit line connections and word line connections in the circuit block are determined based on matches found during the matching.

Abstract: A method and circuit for performing CRC calculations permits variable width data input. Preferably, multiple CRC calculations are performed in parallel, each CRC calculation involving a different number of data bits from the data word and terminating within one clock cycle. The CRC polynomial is preferably incorporated into the hardware for each CRC calculation.

Abstract: The present invention provides a method of design based process control optimization. In an embodiment, the method of design based process control optimization includes creating a circuit layout database including a design rule set. At least one algorithm is employed to query the circuit layout database to calculate at least one process specification limit. The method includes comparing the calculated at least one process specification limit with at least one predefined technology process tool capability to determine if the calculated at least one process specification limit allows for a manufacturable process. If the calculated at least one process specification limit does not allow for the manufacturable process, the limit may be re-optimized.

Abstract: A method and/or an apparatus of power ring positioning to minimize crosstalk are disclosed. In one embodiment, a method includes generating an array of fingers between a power ring and a die, applying a signal wire between a bond pad of the die and a particular finger of the array of fingers, and applying a shielding wire between an adjacent bond pad and the power ring, such that the shielding wire is longer than the signal wire and does not couple to any of the array of fingers. The shielding wire may be placed between adjacent ones of the signal wire to minimize crosstalk between the adjacent ones of the signal wire.

Abstract: The present invention is a method for data path voltage and temperature compensation. The method includes configuring an offline data path to match an online data path. The method further includes compensating the offline data path for voltage and temperature variation. The method further includes swapping the offline data path with the online data path. Further, swapping occurs automatically without interruption of data flow along the data paths.

Abstract: A pixel signal of Bayer pattern output from an imaging device is subjected to interpolation in a pixel interpolation circuit, and converted into a YCbCr signal in a color space conversion circuit. A chroma value calculation circuit calculates a chroma value based on the pixel signal output from the imaging device. A look-up table converts the chroma value into a suppression signal. More specifically, when the chroma value is lower than a threshold value, the look-up table outputs a value lower than 1 as the suppression signal. The suppression signal is corrected in another look-up table, and then, works on Cr and Cb signals in multipliers. A signal in a low-chroma region is thereby suppressed.

Abstract: A platform application specific integrated circuit (ASIC) including a base layer. The base layer generally comprises a predefined input/output (I/O) region and a predefined core region. The predefined input/output (I/O) region may comprise a plurality of pre-diffused regions disposed in the platform ASIC. The predefined core region may comprise one or more metal layers defining a plurality of power regions formed according to a custom design created after the base layer is fabricated. The base layer can be customized by depositing one or more metal layers.

Abstract: The present invention is directed to methods for defining and naming iSCSI targets using volume access and security policy. In an exemplary aspect of the present invention, a method for defining an iSCSI target using volume access and security policy may include the following steps. One or more volumes of a network entity may be first mapped to an initiator. The mapping defines the unique Logical Unit Number for the volume to an initiator. Then, a security level may be defined for access to each volume accessed by the initiator. The subset of mappings for each initiator may be given any unique name. Next, the mapping and security subsets may be used to define the fully qualified targets with which the initiator may open a session.

Abstract: A method and apparatus for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a second set of the pins with unknown ramptime values. One or more closed loops are identified by backtracking from the pins in the second set with unknown ramptime values. A ramptime value for each pin in the one or more closed loops is calculated iteratively.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal oscillating at a frequency in response to a first control signal and a second control signal. The second circuit may be configured to generate the second control signal in response to (i) an input voltage and (ii) the output signal. The second circuit (i) generates the second control signal by comparing a peak voltage of the output signal to the input voltage and (ii) adjusts an amplitude of the control signal in response to the comparison.

Abstract: A method for display compositing is disclosed. The method generally includes the steps of (A) generating a plurality of respective color values and a plurality of respective blending values for a plurality of graphics pixels to be blended with a display picture, (B) examining in a sequence a plurality of neighboring pixels of the graphics pixels adjoining a current pixel of the graphics pixels, the current pixel having a current color value of the respective color values and a current blending value of the respective blending values and (C) replacing the current color value with the respective color value for a particular pixel of the neighboring pixels where (i) the respective blending value for the particular pixel comprises one of a plurality of non-transparent values and (ii) the current blending value comprises one of at least one transparent value.

Abstract: A method of power optimization in a memory is disclosed. The method generally includes the steps of (A) dividing a plurality of bit cells in a design of the memory into (i) a plurality of first rows storing programmed data and (ii) at least one second row storing only padding data, (B) adjusting the design such that a second power consumption in each of the second rows is lower than a first power consumption in each of the first rows and (C) generating a file defining the design as adjusted.

Abstract: Disclosed is a method for creating a large-scale storage array by combining multiple mid-range storage arrays via a host based aggregation engine software application. Each mid-range storage array, also call a storage building block, consists of one or more RAID volumes. Each mid-range storage array has equivalent configuration and property settings including number of drives, RAID level, volume segment sizes, and volume cache settings, but not including the volume label. The complex combination of mid-range storage arrays appears as a single storage system to a data management application of a host computer system. Once the mid-range storage arrays are aggregated into a large-scale storage array, or storage complex array, common features may be modified as a collection of items so that a common modification need only be entered one time for all items in the collection.

Abstract: A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.

Abstract: Several code detectors in parallel simultaneously examine varying overlapping segments of a data stream containing variable length codes, referred to as a data window. The data window segments directly address memory structures within each of the code detectors without any previous logic stages. Each code detector is responsible for a range of code lengths, and ignores data window bits that are not relevant to its code length range. Each code detector outputs a possible result to a layer of logic that selects the possible result of the single code detector which contains result data corresponding to a variable length code in the data window.

Abstract: The present invention provides a memory device of a type that outputs a ready signal to the outside, and that is capable of achieving an enhanced data transfer rate and a uniform latency time. A memory device according to the present invention includes a ready signal sending portion, and the ready signal sending portion monitors a memory portion to detect the memory portion becoming ready for reading or writing of specified data. The ready signal sending portion generates a first ready signal that changes from a busy state to a ready state after the detection and an enabling signal that changes from a disable state to an enable state on the basis of a preset ready generating timing value. When the first ready signal is in the ready state and the enabling signal is in the enable state, the ready signal sending portion sends to the outside a second ready signal that is in a ready state.

Abstract: The invention provides a number of related methods which improve the test and analysis of integrated circuit devices. A first method of the invention provides a method for pausing on a SCAN based test. A second method of the invention provides a method for using stimulations and responses of a known good device to increase fault coverage of patterns in a test flow. A third method of the invention provides a method to curve trace device buffers on an ATE.

Abstract: A semiconductor chip is provided which includes active and inactive IP cores. The spaces on the metal layer associated with the inactive IP cores includes voltage contrast inspection structures. The voltage contrast inspection structures serve to provide improved planarization of the metal layer and provided improved inspection capabilities.