Patents Assigned to LSI
  • Integrated circuit package and system interface
    Patent number: 7550839
    Abstract: An apparatus for enhancing the performance of an IC package and media interface. Adding a fissure to a Flip-Chip type package improves the crosstalk performance of the package for both high and low frequencies. The wall of the fissure can be implemented with a heat spreader layer and can be connected to any AC ground such as VSS or VDD package planes. The fissures can also accommodate the ingress of an optical fiber, which allows for a direct interface with the transceivers. The direct optical fiber interface permits the removal of solder balls for high speed signal traces, with their respective vias. On-chip integrated LEDs or other similar light source transceivers can drive the high speed signal media. Selective deposition of low dielectric material can also improve the frequency response of high speed signal package traces.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: June 23, 2009
    Assignee: LSI Corporation
    Inventors: Frantisek Gasparik, Steve Callicott
  • MOMENT COMPUTATION ALGORITHMS IN VLSI SYSTEM
    Publication number: 20090158228
    Abstract: An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph. the elimination process is performed based upon the degree of the nodes. By eliminating nodes in this fashion, the computation complexity is significantly reduced. With this elimination process, resistor loops and crossed loops can also be solved. The order in which the nodes are eliminated is optimized using the depth-first-search method on the parasitic graphs, further reducing the computation complexity. The method provides a consistent functional interface, applicable to different circuit model structures. In addition, the method accounts for coupling capacitance between interconnects.
    Type: Application
    Filed: December 19, 2008
    Publication date: June 18, 2009
    Applicant: LSI CORPORATION
    Inventors: Weiqing Guo, Sandeep Bhutani
  • Sequential tester for longest prefix search engines
    Patent number: 7548844
    Abstract: The present invention is directed to a sequential tester for longest prefix search engines. The tester may include a longest prefix search engine, an inputs generator for providing a nearly random flow of input commands to the longest prefix search engine and for outputting a floating rectangle which may represent a search table of the longest prefix search engine, a coding module for providing address and prefix information to the longest prefix search engine, a mapping module for providing data information to the longest prefix search engine, a super search engine for performing super search operations, and an analyzer for computing predicted outputs of the longest prefix search engine and for comparing the predicted outputs with actual outputs computed by the longest prefix search engine.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: June 16, 2009
    Assignee: LSI Logic Corporation
    Inventors: Alexander E. Andreev, Anatoli A. Bolotov
  • Capacitance detecting proximity sensor
    Patent number: 7545153
    Abstract: A capacitance detecting proximity sensor forms a proximity detection range in a spatially open region, avoids the effects resulting from peripheral objects outside the detection target, and enables proximity detection with few malfunctions. The proximity sensor includes: a first detection electrode and a second detection electrode that are disposed to have a predetermined range difference h with respect to a detection direction Y in which a detection subject comes into proximity to the proximity sensor and are independent from a ground potential; and a proximity detection circuit that outputs, as a proximity detection output, the difference between a capacitance to ground Ca formed by the first detection electrode and a capacitance to ground Cb formed by the second detection electrode.
    Type: Grant
    Filed: December 25, 2003
    Date of Patent: June 9, 2009
    Assignee: ACT · LSI Inc.
    Inventor: Hiroshi Abe
  • Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage
    Patent number: 7546568
    Abstract: A method for designing an integrated circuit is disclosed. The method generally comprises the steps of (A) splitting a design layout of the integrated circuit into a plurality of tiles, (B) adding a plurality of tie-to cells to the design layout, wherein at least one of the tie-to cells generating a tie-to signal at a particular logical level is added into each of the tiles having at least one gate with an input fixed to the particular logical level and (C) routing the tie-to signal to each of the inputs within each of the tiles.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: June 9, 2009
    Assignee: LSI Corporation
    Inventors: Juergen Dirks, Matthias Dinter, Ralf Leuchter
  • Low jitter and/or fast lock-in clock recovery circuit
    Patent number: 7545900
    Abstract: An apparatus comprising an oscillator circuit, a control circuit, a counter circuit and a detector circuit. The oscillator circuit may be configured to generate an output signal oscillating at a particular frequency in response to a control signal. The control circuit may be configured to generate the control signal in response to a first error signal and a second error signal. The counter circuit may be configured to generate the first error signal in response to the output signal and an input signal. The detector circuit may be configured to generate the second error signal in response to the output signal and the input signal.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: June 9, 2009
    Assignee: LSI Corporation
    Inventors: Ho-Ming Leung, Nasima Parveen, Ka-Shu Ko
  • Optimization of flip flop initialization structures with respect to design size and design closure effort from RTL to netlist
    Patent number: 7546560
    Abstract: A method for optimizing a design of a circuit is disclosed. The method generally includes the steps of (A) identifying a plurality of first flip flops in the design and (B) replacing each of the first flip flops in a file of the design that do not have to be initialized during operations of the circuit with a respective second flip flop without an initialization capability.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: June 9, 2009
    Assignee: LSI Corporation
    Inventors: Juergen Dirks, Martin Fennell, Iain Stickland
  • Low power on-chip global interconnects
    Patent number: 7545205
    Abstract: An apparatus including a first circuit, a second circuit and a third circuit. The first circuit may be configured to (a) receive (i) a plurality of input signals and (ii) a clock signal and (b) present (i) a plurality of low-swing differential signals and (ii) a full-swing differential signal. The second circuit may be configured to (a) receive (i) the plurality of low-swing differential signals, (ii) the full-swing differential signal and (iii) the clock signal and (b) present a plurality of output signals. The third circuit may be configured to communicate the plurality of low-swing differential signals and the full-swing differential signal from the first circuit to the second circuit. The third circuit may be further configured to generate a local clock in response to the full-swing differential signal.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: June 9, 2009
    Assignee: LSI Corporation
    Inventors: Robin Tang, Ephrem C. Wu
  • Built in self test transport controller architecture
    Patent number: 7546505
    Abstract: A built in self test circuit in a memory matrix. Memory cells within the matrix are disposed into columns. The circuit has only one memory test controller, adapted to initiate commands and receive results. Transport controllers are paired with the columns of memory cells. The controllers receive commands from the memory test controller, test memory cells within the column, receive test results, and provide the results to the memory test controller. The transport controllers operate in three modes. A production testing mode tests the memory cells in different columns, accumulating the results for a given column with the controller associated with the column. A production testing mode retrieves the results from the controllers. A diagnostic testing mode tests memory cells within one column, while retrieving results for the column.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: June 9, 2009
    Assignee: LSI Corporation
    Inventors: Sergey Gribok, Alexander Andreev, Ivan Pavisic
  • SPREAD SPECTRUM CLOCK GENERATOR CAPABLE OF FREQUENCY MODULATION WITH HIGH ACCURACY
    Publication number: 20090141774
    Abstract: In a spread spectrum clock generator, a DLL circuit delays an oscillation clock signal from a VCO and outputs ten delay clock signals having different phases respectively. A selector selects any one of the ten delay clock signals, and outputs a selected clock signal. A control circuit controls a signal selection operation of the selector. A feedback frequency divider divides a frequency of the selected clock signal by a frequency division ratio N, and generates a comparison clock signal. In this manner, a phase of the comparison clock signal can be fine-tuned. Therefore, a spread spectrum clock generator capable of frequency modulation with high accuracy can be obtained.
    Type: Application
    Filed: February 4, 2009
    Publication date: June 4, 2009
    Applicants: RENESAS TECHNOLOGY CORP, RENESAS LSI DESIGN CORPORATION
    Inventors: Masahiro ARAKI, Chieko Hayashi
  • Staged Scenario Generation
    Publication number: 20090144679
    Abstract: A method of verifying integrated circuit designs, by constructing a series of atomic generators in a staged, hierarchical order, applying a lowest of the hierarchical generator stages to device level test cases of the verification process, applying a highest of the hierarchical generator stages to system level test cases of the verification process, reusing code written for and used in the lowest hierarchical generator stage in a next higher generator stage, creating a constraint scenario in the highest hierarchical generator stage, and injecting the constraint scenario into a next lower generator stage.
    Type: Application
    Filed: December 3, 2007
    Publication date: June 4, 2009
    Applicant: LSI CORPORATION
    Inventors: Sidhesh Patel, Prakash Bodhak
  • Simulated battery logic testing device
    Patent number: 7542858
    Abstract: A simulated battery test device and method that is capable of testing a battery charging circuit and logic circuit to determine proper operation. An operational amplifier is used that can both source and sink current to simulate the operation of the battery. A battery low signal can be generated using the simulated battery test device to test a battery charging circuit and logic circuit in a battery low condition. In addition, a battery open signal can be generated to test the battery charging and logic circuit in a battery open condition. Charging currents are detected to determine if currents fall within an acceptable range.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: June 2, 2009
    Assignee: LSI Corporation
    Inventors: Randall F. Horning, Edde Tin Shek Tang, Del Fafach, Jr.
  • Continuous-time decision feedback equalizer
    Patent number: 7542508
    Abstract: A continuous-time domain Decision Feedback Equalizer (DFE) for use in a serial communication channel comprises in one embodiment a summer, a decision circuit, a capture flip-flop (FF) and an N-th order active filter. The DFE and its active filter operate in continuous time to give improved performance over a discrete-time DFE. In one embodiment involving a first-order active filter, the capture FF is outside the continuous-time negative feedback loop of the DFE and involves a differential signal amplifier. In another embodiment, the capture flip-flop is inside the DFE loop, and in a third embodiment the decision circuit comprises a comparator.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: June 2, 2009
    Assignee: LSI Logic Corporation
    Inventors: Mark J Marlett, Mark Rutherford
  • I/O planning with lock and insertion features
    Patent number: 7543261
    Abstract: A method of operation for an input/output assignment tool is disclosed. The method generally includes the steps of (A) generating a graphic presentation to a user displaying (i) a circuit icon having a plurality of pin icons and (ii) a plurality of signal icons, (B) moving a first of the signal icons within the graphic presentation to a first of the pin icons in response to a move command from the user and (C) indicating an acceptance of an association between the first signal icon and the first pin icon in response to the association passing a rule.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: June 2, 2009
    Assignee: LSI Corporation
    Inventors: Grant Lindberg, Gregor J. Martin, David Asson, Ying Chun He
  • ADJUSTABLE HOLD FLIP FLOP AND METHOD FOR ADJUSTING HOLD REQUIREMENTS
    Publication number: 20090134912
    Abstract: A method and apparatus are provided for storing a value in a process register of an electrical circuit, which indicates a strength of a process in which the circuit was fabricated, and adjusting an input delay applied to data signals received by a synchronous storage element of the electrical circuit based on the stored value.
    Type: Application
    Filed: November 23, 2007
    Publication date: May 28, 2009
    Applicant: LSI Corporation
    Inventors: Stephan Habel, Stefan G. Block
  • Image filter, image filtering method and computer program
    Patent number: 7539352
    Abstract: A first pixel group containing a pixel of interest, a second pixel group containing the first pixel group, and a third pixel group containing the second pixel group are defined. A first reference pixel value is calculated based on the first pixel group, and a second reference pixel value is calculated based on the third pixel group. The second pixel group is divided into two sub-groups with respect to the second reference pixel value. The sub-group containing the pixel of interest is selected as a target set. In the target set, a pixel with a pixel value close to the first reference pixel value is selected as a corrective pixel. The pixel value of the pixel of interest is replaced with the pixel value of the corrective pixel.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: May 26, 2009
    Assignee: MegaChips LSI Solutions Inc.
    Inventors: Hiromu Hasegawa, Munehiro Mori, Nobuhiro Minami
  • Revision control for database of evolved design
    Patent number: 7539680
    Abstract: The invention relates to a method of controlling access to a database of a design. The method may comprise the step of identifying a version of the design by a first identifier, allocating first authorization information to the first identifier, and controlling access to the database. The first authorization information may indicate a permission of one or more users to access information in the database in respect of the first identifier. The access may be controlled in accordance with the first authorization information.
    Type: Grant
    Filed: May 10, 2002
    Date of Patent: May 26, 2009
    Assignee: LSI Corporation
    Inventor: David Tester
  • Route aware Serial Advanced Technology Attachment (SATA) Switch
    Patent number: 7539797
    Abstract: A switch is coupled between a plurality of host units and a device for routing frame information therebetween. The switch includes a first serial advanced technology attachment (ATA) port including a first host task file that is responsive to a non-data frame information structure (FIS) from a first host unit. The switch further includes a second serial ATA port including a second host task file that is responsive to a non-data FIS from a second host unit. The switch further includes a third serial ATA port that is responsive to a non-data FIS from a device and further includes an arbitration and control circuit for selecting one of the first host or second host units to concurrently access the device, through the switch, by accepting non-data FIS, from either of the first or second host units, at any given time, including when the device is not in an idle state.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: May 26, 2009
    Assignee: LSI Corporation
    Inventors: Siamack Nemazie, Andrew Hyonil Chong
  • Mitigating performance degradation caused by a sata drive attached to a sas domain
    Patent number: 7539798
    Abstract: The present invention provides a device and method for mitigating performance degradation caused by SATA drives attached to a SAS domain. In one of the embodiments of the present invention, a SATA degradation mitigation device (“SDMD”) is installed between a SAS domain and one or more SATA drives. The SDMD effectively reduces congestion on intermediate links by buffering SATA data and transmitting the data at a rate which is higher than the rate at which the SATA data is received from a drive. Conversely, write data from the SAS domain may be buffered at the SDMD at a higher rate and subsequently sent to the SATA drive at a lower rate. This SATA data buffering and subsequent increase in data rate improves the overall efficiency of a SAS domain storage system by reducing data congestion arising out of low-performance SATA drives clogging the intermediate links.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: May 26, 2009
    Assignee: LSI Logic Corporation
    Inventors: William Voorhees, Jason Williams
  • Foldable support for domed illumination element
    Patent number: D594591
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: June 16, 2009
    Assignee: LSI Industries, Inc.
    Inventors: John Delmore Boyer, Mark C. Reed