Abstract: An apparatus comprising a photo diode array, a differential push-pull generator circuit and an attenuation prediction circuit. The photo diode array may be configured to generate a plurality of beam signals. The differential push-pull generator circuit may be configured to generate a differential push-pull signal with one or more gain blocks in response to (i) a plurality of input signals, (ii) a gain approximation signal and (iii) the plurality of beam signals. The attenuation prediction circuit may be configured to (i) predict an attenuation factor of the differential push-pull signal and (ii) generate the gain approximation signal in response to (a) a plurality of amplification signals and (b) a plurality of angle signals.

Abstract: An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph. The elimination process is performed based upon the degree of the nodes. By eliminating nodes in this fashion, the computation complexity is significantly reduced. With this elimination process, resistor loops and crossed loops can also be solved. The order in which the nodes are eliminated is optimized using the depth-first-search method on the parasitic graphs, further reducing the computation complexity. The method provides a consistent functional interface, applicable to different circuit model structures. In addition, the method accounts for coupling capacitance between interconnects.

Abstract: A solid-state imaging device and a camera system are disclosed. The solid-state imaging device includes a pixel unit and a pixel signal readout circuit. The pixel signal readout circuit includes a plurality of comparators disposed to correspond to a pixel column array, and a plurality of counters. Each counter includes a first amplifier, a second amplifier, and a mirror circuit to from a current mirror in parallel with the second amplifier. The first amplifier includes differential transistors, initializing switches connected between gates and collectors of the differential transistors, and first and second capacitors connected to each of the gates of the differential transistors. The second amplifier includes an initializing switch and a third capacitor. The mirror circuit includes a gate input transistor whose gate is inputted with a voltage sampled by the first amplifier or a voltage sampled by the second amplifier.

Abstract: A memory testing system for testing a plurality of memory locations in an electronic memory device is provided. The system includes a programmable memory device integrated into the electronic memory device capable of receiving and storing a compiled memory testing program. A processor is in communication with the programmable memory device to read and execute instructions from the compiled testing program stored in the programmable memory device and a command interpreter is configured to receive data from the processor related to commands to be executed during memory testing.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of digital intermediate signals in response to an analog input signal, a first set of threshold and reference voltages and a second set of threshold and reference voltages, where the threshold and reference voltages of the first set are shifted with respect to corresponding threshold and reference voltages of the second set. The second circuit may be configured to generate a digital output signal in response to the plurality of digital intermediate signals.

Abstract: Multiple inductor structures and methods for providing low mutual inductance between the inductors are described. In various embodiments of the invention, the polarities of the inductors are positioned such that parasitic mutual inductance is reduced by causing electro-magnetic fields to at least partially cancel resulting in a reduction in interference between the inductors. The polarities of the magnetic fields produced by each inductor are opposite to each other so that at least a partial cancellation results when the fields interfere with each other.

Abstract: A method for securing a content is disclosed. The method generally includes the steps of (A) generating a media key by decrypting a media key block based on a device key unique to a particular player of a plurality of players, (B) modifying the media key by decryption based on a class key such that the media key is unique for each of a plurality of subscriber classes, (C) writing an encrypted title key in a media by encrypting a title key based on both the media key after modification and a media identification value unique to the media and (D) writing an encrypted content in the media by encrypting the content based on the title key.

Abstract: A system, apparatus and method for maintaining information related to a write operation is described. In one embodiment of the invention, a write journal is provided that contains a list of entries that store information related to active write operations so that a particular write may be restarted in order to correct an inconsistency. The journal may have a battery backed cache, in which data is stored prior to writing to a disk, which is provided power in the case of a power failure. The journal may be located in memory positioned at various locations within a system including on a controller card for a disk array system or on a motherboard of a host system.

Abstract: Different ways to reduce or eliminate the IMC cracking issues in wire bonded parts, including: changing to more compressive dielectric films for top, R1, and R2; changing the top passivation film stacks to more compressive films; changing the low k film to a higher compressive film; reducing the R layer thickness and pattern density to reduce tensile stress; and minimizing anneal and dielectric deposition temperatures. Each of the methods can be used individually or in combination with each other to reduce overall tensile stresses in the Cu/low-k wafer thus reducing or eliminating the IMC cracking issue currently seen in the post wire bonded parts.

Abstract: A method for controlling an output phase of a phase interpolator, by forming an M bit control word, designating N bits of the control word as a fractional number portion, designating M-N bits of the control word as a whole number portion, adjusting a phase jump of the phase interpolator at a designated clock cycle by a first number of phases as designated by the whole number portion plus a second number of phases as designated by the fractional number portion. The designated clock cycle can be identified by numbering clock cycles with a count value from counter having a repeating period of 2N, and for each clock cycle identified by a multiple of the count value of 2k within the repeating period, where k is a bit-wise position within the fractional number portion having a value of 0?k?N-1, the second number of phases can equal a binary value of the fractional number portion at the kth position, for any k.

Abstract: A system, apparatus and method for storing and maintaining drive configuration data related to disk drives within a RAID. In one embodiment of the invention, configuration data is stored external to the disk drives within the RAID. A scan(s) is performed of the RAID disk drive configuration and/or configuration data on the disk drives. Mismatches or errors within the RAID disk drive configuration may be corrected using the configuration data stored external to the RAID disk drives.

Abstract: Methods and systems for improved lock processing in a storage controller. Storage controllers that provide storage management features such as RAID storage controllers may concurrently process I/O requests received from attached host systems and I/O requests generated internally by the management processing in the controller. Such concurrent processing is coordinated by lock processing that allows affected storage areas to be locked during processing of an I/O operation. Features and aspects hereof allow such lock processing to lock regions flexibly defined by the controller. The flexible definition of the regions to be locked allows variance in the granularity of the locks required. Smaller granularity permits more concurrent I/O requests to be processed.

Abstract: A data-processing apparatus, method and program product generally include identifying one or more SAS expanders and one or more link thereof associated with an SAS domain of a data-processing apparatus. Link and reset data can be automatically injected onto the link(s) and the SAS expander(s) associated with the SAS domain, in response to identifying the SAS expander(s) and one or more links thereof. The presence of the link(s) within the SAS domain can then be verified, in response to automatically injecting the link and reset data onto one or more links and one or more SAS expanders in order to test the links and the SAS expanders associated with the SAS domain.

Abstract: A zero automated electrical testing (ATE) interposer daughter card (IDC) is provided for use in a test apparatus for ATE. Embodiments of the IDC include a first side having a first set of pads for mounting I/O's of a test package; and a second side having a second set of pads coupled to the first set of pads for replicating the first set of pads, wherein the second set of pads is located in area of the interposer card horizontally offset from the first set of pads, such that ATE measurements are obtained by removably inserting only a portion of the interposer card containing the second set of pads into an ATE test socket.

Abstract: Apparatus and associated methods for a simplified Serial SCSI Protocol (“SSP”) link layer within a SAS device. Features and aspects hereof provide a simplified SSP link layer processor to enable cost reduction and simplification of Serial Attached SCSI (“SAS”) devices requiring only limited SSP exchange functionality. In one embodiment, a SAS expander may incorporate the simplified SSP link layer features and aspects hereof to permit simple management of SAS devices coupled to the expander or coupled downstream through other expanders. The simplified SSP link layer suffices for simple SAS management functions while reducing cost and complexity of the SAS expander. Features and aspects hereof may be implemented with minimal customized circuits for SSP link layer management in the SAS device. In one aspect hereof, the simplified link layer processing may be implemented as a simplified state machine model in combinatorial logic coupled with any requisite memory components.

Abstract: A metallic reflector device having one or an array of individual reflector elements for positioning over a corresponding one or array of light sources, preferably comprising one or more light emitting diodes (LEDs). The metallic reflector device includes a planar base and a plurality of the reflector elements. The planar base has one or a plurality of apertures, each aperture having an edge that defines a proximal rim of the reflector element. Each reflector element includes an annular sidewall having an inner surface that extends from the proximal annular rim to a distal annular rim. The proximal annular rim defines a first opening through which direct and reflected light from a light source is emitted. The distal annular rim defines a second opening through which the light source is disposed. The inner surface of the annular sidewall is formed from the material of the planar sheet by mechanically deforming the planar sheet, such as by stamping or drawing.

Abstract: A lighting apparatus having a pivotable light cartridge for positioning and directing the light output of a plurality of light sources, the light cartridge including an elongated base oriented along the longitudinal axis, a pivot at the opposed first and second ends of the light cartridge along the longitudinal axis, a plurality of light sources, and an longitudinal wall extending from the lateral edge of the base, the wall including a plurality of spaced-apart, radially-extending ribs, each having a distal edge. A rotatable worm gear having a helical thread is positioned in mechanical engagement with a portion of the distal edges of the plurality of ribs, so that rotation of the worm gear with a hand tool effects pivoting of the light cartridge along the longitudinal axis.

Abstract: A system, apparatus and method for delaying a signal, such as a high-speed signal are disclosed. A multi-stage delay cell is described in which the amount of delay applied to a signal depends on which stages are activated within the cell. In various embodiments of the invention, noise caused by transitions between various delay times within the cell is reduced by efficiently managing voltage states on each of the stages.

Abstract: A hard disk drive is coupled to a plurality of host units for communication. The first host unit includes a serial advanced technology attachment (SATA) port, including a first host task file coupled for access to the device and responsive to commands sent by the first host unit. The second host unit includes a SATA port, including a second task file, coupled for access to the device and responsive to commands sent by the second host unit. An arbitration and control circuit is coupled to the first host task file and second task file. The arbitration and control circuit selects commands from one or the other host units when either host units sends a command for execution for concurrently accessing the device, and accepts commands from both, at any given time, including when the device is not idle.

Abstract: A method for conserving power in a device is disclosed. The method generally includes the steps of (A) storing a plurality of data items in a plurality of bit cells in the device such that a majority of the bit cells holding the data items have a first logic state, wherein reading one of the bit cells having the first logic state consumes less power than reading one of the bit cells having a second logic state; (B) generating a polarity signal by analyzing the data items, the polarity signal indicating that the data items are stored in one of (i) an inverted condition and (ii) a non-inverted condition relative to a normal condition; and (C) driving at least one of the data items onto an external interface of the device in the normal condition during a read operation based on the polarity signal.