Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The package includes a ESD shield attached to the substrate. The ESD shield configured to increase the ESD hardness of the package. The ESD shield can further serve to stiffen the package to prevent warping and operate as a heat spreader.

Abstract: A test system tests a circuit. Compressed scan data subsets are stored, one at a time, in a memory of the test system. The multiple compressed scan data subsets correspond with multiple scan chains in a function block of the tested circuit. Transmission of the compressed scan data subset from the memory to the tested circuit is controlled by the test system. The test system receives a compacted test pattern subset from the tested circuit and provides a test system output that indicates a presence of any errors in functioning of the tested circuit.

Abstract: A device for holding and positioning an optic, such as a refractive lens, over a light source such as a light emitting diode. The refractive lens is frustum-shaped with an upper light-exiting end having an upper rim, a lower light-entering end, and a conical sidewall that tapers from the upper rim to the lower end. The device has a channel including a base and first and second sidewalls extending from the opposed side edges of the base, and further having one or more optic holding positions. The optic holding position includes an aperture formed in the base that is configured to receive the conical sidewall of the optic, and an aperture formed in a portion of each sidewall, adjacent the aperture in the base, for retaining a portion of the upper rim of the optic lens. The aperture can include a slot opening through which a portion of the upper rim of the optic lens at least partially extends.

Abstract: A system generally including a clock structure analysis tool, a static timing analysis tool and a waveform tool is disclosed. The clock structure analysis tool may be configured to generate a simplified clock structure for a clock signal in a complex clock structure in a design of a circuit. The static timing analysis tool may be configured to generate a plurality of results for a plurality of intermediate signals in the simplified clock structure in response to a static timing analysis of the design. The waveform tool may be configured to generate a first representation in a graphical user interface format of the intermediate signals and the results.

Abstract: A switch is coupled between a plurality of host units and a device, for communicating therebetween. A first serial advanced technology attachment (SATA) port includes a first host task file, and is coupled to a first host unit. A second SATA port includes a second host task file, and is coupled to a second host unit. The task files are responsive to commands sent by the respective host units, and cause access to the device by the host respective host units. A third parallel ATA port includes a device task file, and is coupled to a device, for access to the device by the first or second host units. An arbitration and control circuit is coupled to the task files, for selecting one of the first or second host units to concurrently access the device through the switch at any given time, including when the device is not idle.

Abstract: A switch is coupled between a plurality of host units and a device for communicating therebetween. Included is a first serial advanced technology attachment (SATA) port, a second SATA port, and a third SATA port. The first SATA port includes a first host task file coupled to a first host unit, and the first host task file is responsive to commands sent by the first host unit to the device. The second SATA port includes a second host task file coupled to a second host unit, and the second host task file is responsive to commands sent by the second host unit to the device. An arbitration control circuit is coupled to the SATA ports, and selects from the first and second hosts to concurrently access the device, through the switch, accepting commands from either host units at any time, including when the device is not idle.

Abstract: A method of designing a logic circuit based on one of the functions of the form fn=x1 (x2 & (x3 (x4 & . . . xn . . . ))) and f?n=x1 & (x2 (x3 & (x4 . . . xn . . . ))), by (a) selecting n as the number of variables of the logic circuit, (b) testing n against a threshold, (c) for values of n less than the threshold, using a first algorithm to design the logic circuit, (d) for values of n greater than the threshold, using a second algorithm to design the logic circuit.

Abstract: A method and apparatus position a beam spot on a recording medium. The positioning includes (a) observing a first center error in a first closed loop control during tracking mode, the first center error including a repeatable run out (RRO) error, (b) estimating a center error (CE)-RRO from the first center error, the CE-RRO being part of the first center error caused by the RRO, (c) observing a second center error in a second closed loop control during a rough seek, (d) subtracting the CE-RRO from the second center error, (e) controlling the beam spot based on the second center error less the CE-RRO during the rough seek, and (f) adding an open loop control to the second closed loop control during the rough seek, the added open loop control inducing a motion of the lens relative to an optical center of the OPU during the rough seek.

Abstract: An externally adjustable directional canopy luminaire is disclosed that may be easily and quickly adjusted from the outside of its housing to direct light toward a particular target area. The luminaire includes a lamp shroud assembly including a door frame, a shroud and a lamp socket which is connectable to an electrical power source to power a replaceable lamp, an external adjustment member, and an internal mechanism movably connected to the external adjustment member through the shroud and indirectly connected to a portion of the lamp socket, wherein adjustment of the external adjustment member can alter the angle of direction of the lamp socket and thus the direction of light emitted from the replaceable lamp through the opening of the shroud.

Abstract: An apparatus and method are provided for powering an integrated circuit chip with a supply voltage generated externally to the chip. An on-chip clock signal is generated with a ring oscillator fabricated on the integrated circuit chip. The supply voltage is altered as a function of a difference between a frequency of the on-chip clock signal and a reference clock frequency.

Abstract: Embodiments of the present invention provide a multi-fan cooling system in which redundancy in airflow across a plurality of electrical boards is maintained. This redundancy is provided by having an ability to at least partially divert airflow from a functioning fan to an electrical board for which its corresponding fan has failed. According to various embodiments of the present invention, the multi-fan cooling system comprises two fans located proximate to each other. An airflow plenum couples and distributes air from the two fans across a plurality of electrical boards. In certain embodiments, the plenum comprises stacked outlets that distribute airflow from the two fans across the plurality of electrical boards. During normal operation, this airflow is approximately evenly distributed across the electrical boards. However, if one of the fans fails, the plenum causes air from the single operating fan to still be distributed across the plurality of electrical boards.

Abstract: A method of analyzing multimode delay in an integrated circuit design to produce a timing model for the integrated circuit design, by inputting a net list, IO arc delays, interconnection arc delays, and constant nets with assigned Boolean functions for the integrated circuit design, propagating the constant nets and assigning Boolean conditions to the IO arc delays and the interconnection arc delays, evaluating timing path delays and conditions for the integrated circuit design, creating the integrated circuit design timing model parameters, and outputting the integrated circuit design timing model. The method is especially desirable for netlists with very complicated mixing logics that include muxing of clocks. In particular, RRAMs are such netlists.

Abstract: In contrast to prior are solutions that conduct an averaging operation to estimate metrics related to a communications channel such as a signal-to-noise ratio, the present invention selects a particular value such as a minimum, maximum, or median value from a distribution of values collected over a selected interval. Selecting a particular value from the distribution of values facilitates a more accurate characterization process and increased data throughput. To reduce the processing burden associated with selecting a particular value, the present invention provides a set of cascaded value selection queues that each selects a particular value from the queued values such as a minimum value. The cascaded queues are also successively sub-sampled to reduce the computing resources required to characterize the communications channel. The estimated metrics resulting from the above-described process may be used to adjust the data encoding process and increase data throughput on the communications channel.

Abstract: The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.

Abstract: Methods and systems for customizing information in a memory associated with a SAS host bus adapter (“HBA”). A SAS HBA typically includes a memory component that stores information common to all SAS HBA's manufactured by a particular vendor (e.g., common instructions and data). In addition, each HBA memory component typically includes some information unique to each HBA (e.g., board trace number, SAS address, configuration page, boot record, etc.). Features and aspects hereof permit pre-programmed memory components to be integrated with a SAS HBA to eliminate a step to program an assembled HBA through a specialized, one-time interaction to add required unique information. Thus a manufacturer may simply integrate a pre-programmed memory component to an otherwise completed HBA assembly to complete the product manufacturing without need for a special programming step. Or a design or test engineer may simply replace a memory component to change unique information on the HBA.

Abstract: A directional canopy luminaire that can be easily and quickly adjusted to direct light from a canopy toward a particular target area without scattering light to unintended areas. The luminaire includes an outer housing having an aperture, a directional support rotatably mounted within the outer housing, an inner support pivotally affixed to the directional support, and a light supporting means. The light supporting means is typically configured to support a replaceable lamp that is electrically connectable to an electric power source. Light can be aimed in any desired direction through the aperture of the luminaire by pivoting into a position the directional support and the inner support.

Abstract: A method for classifying a first video type and a second video type in a digital video signal having a series of frames is disclosed. The method generally includes a first step of (A) reading a first set of parameters defining an active portion of a first of the frames. A second step may involve (B) reading a second set of parameters defining an active portion of a second of the frames. A third step includes (C) comparing the first set of the parameters with the second set of parameters to generate a comparison value. As such, (D) if the comparison value is above a predetermined threshold, indicating the first video type and (E) if the comparison value is not above the predetermined value, indicating the second video type.

Abstract: An apparatus comprising an input circuit, a storage circuit and an output circuit. The input circuit may be configured to generate a plurality of data paths in response to an input data signal having a plurality of data items sequentially presented in a first order. The storage circuit may be configured to store each of the data paths in a respective shift register chain. The output circuit may be configured to generate an output data signal in response to each of the shift register chains. The output data signal presents the data items in a second order different from said first order.

Abstract: An apparatus comprising a disk array and a controller. The disk array may be configured to send and receive data from the controller. The disk array generally comprises a plurality of disk drives each configured to store a drive signature. The controller may be configured to (i) receive a data signal and one or more address signals and (ii) present data to the disk array.