Abstract: The tilt and position of individually controllable element are simultaneously adjusted to allow a greater range of contrasts to be achieved. This can also be used to compensate for cupping of individually controllable elements. Simultaneous adjustment of both the position and tilt of the individually controllable elements can be achieved by two electrodes operable over a range of values.

Abstract: A sensor such as a CCD image pickup device is equipped with a color filter of RGB Bayer array. An image is read from such a sensor (S1) and inputted to a color interpolation device as raw data (S2). The color interpolation device calculates additional values DH and DV of differential absolute values of pixel values in a horizontal direction and a vertical direction by using pixels of all colors in a peripheral area of a specified pixel (S3 and S4). The additional values DH and DV are compared with each other (S5) and when it is judged that there is a tendency of pixel drift in the horizontal direction or the vertical direction, S6 is executed. In S6, when a correlation in the vertical direction is strong, an interpolation using vertical adjacent pixels is performed and when a correlation in the horizontal direction is strong, an interpolation using horizontal adjacent pixels is performed. By this method, it is possible to improve the accuracy of color interpolation.

Abstract: Systems and methods for improving performance of a re-synchronization process in a RAID level 1 storage system. In one aspect a local cache memory associated with the second or mirrored disk drive is enabled during the re-synchronization operation but left disabled during normal operation processing host requests. The cache is flushed to the persistent medium of the second disk drive before resuming normal I/O request processing. In another aspect normal I/O request processing is interleaved with portions of the processing for re-synchronization of the mirrored disk drive. Normal I/O request processing proceeds for a first period of time. Re-synchronization processing for a portion of the mirrored information then proceeds (with local cache memory of the mirrored disk drive enabled) for a second period of time.

Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The package includes a ESD shield attached to the substrate. The ESD shield configured to increase the ESD hardness of the package. The ESD shield can further serve to stiffen the package to prevent warping and operate as a heat spreader.

Abstract: A method for representing a motion for two blocks. The method generally includes the steps of (A) exchanging a particular value of a plurality of values with a memory, each of the values defining which of the two blocks use which of a plurality of motion vectors based upon one of a plurality of prediction types and (B) representing the motion for the two blocks with a group comprising the particular value and up to all of the motion vectors.

Abstract: A decoupling circuit disposed between a first rail and a second rail, where a third power rail is disposed between the first and second rails. A resistor having a first electrode and a second electrode is disposed between the first and second rails. Two capacitors are disposed between the first and second rails. The resistor is connected to the third rail and the two capacitors. In this manner, the two capacitors are connected in series with respect to the resistor, and in parallel with respect to one another. A first of the two capacitors is connected to the first rail, and a second of the two capacitors is connected to the second rail. At least one of the resistor and the two capacitors is disposed at least in part beneath the third rail.

Abstract: Programmable nanotube interconnect is disclosed. In one embodiment, a method includes forming a interconnect layer using a plurality of nanotube structures, and automatically altering a route of an integrated circuit based on an electrical current applied to at least one of the plurality of nanotube structures in the interconnect layer. Neighboring interconnect layers separated by planar vias may include communication lines that are perpendicularly oriented with respect to each of the neighboring interconnect layers. The nanotube structure may be chosen from a group comprising a polymer, carbon, and a composite material. A carbon nanotube film may be patterned in a metal layer to form the plurality of nanotube structures. A sputtered planar process may be performed across a trench of electrodes to create the carbon nanotube structures.

Abstract: The present disclosure is directed to a method of selecting cells in an integrated circuit for logic restructuring of an original design. The original design includes a set of parameters. The method includes forming a restructuring set that will include the selected cells for logic restructuring, and a candidate set. The restructuring set includes restructuring cells with an initial cell. The restructuring set is adapted to accept additional cells identified as restructuring cells. The candidate set is adapted to include candidate cells, where each candidate cell in the candidate set is connected to at least one of the restructuring cells in the restructuring set. The candidate set is adapted to remove candidate cells from the candidate set. The restructuring set is adapted to accept selected removed candidate cells as identified restructuring cells if a corresponding parameter is included in the set of parameters.

Abstract: Circuits, systems and methods for improved monitoring of status of a storage controller in a storage system. A monitoring circuit external to the storage controller is adapted to couple to the internal bus structure within the storage controller. The monitoring circuit is adapted to sense status of the storage controller by monitoring bus transactions within the storage controller that indicate status of the control and/or of the storage system. In one aspect the monitoring circuit saves sensed status in a memory associated with the circuit. In another aspect, the monitoring circuit includes a network interface to transmit sensed/saved status to an external data processing system.

Abstract: A method for generalizing design attributes in a design capture environment comprising the steps of (A) defining a procedure for adding one or more auxiliary configurators to a tool or suite of tools, (B) linking the auxiliary configurators to predetermined object points in an abstracted design and (C) defining a procedure for the tool or suite of tools to reference the one or more auxiliary configurators, wherein the auxiliary configurators are neither referenced by a core nor built into the tool or suite of tools.

Abstract: An apparatus and a method for analyzing signals within an integrated circuit are described. In one embodiment of the present invention, internal IC signals are tapped, sampled and stored according to one or more sampling criteria. The signals may be taken from multiple locations within the IC and the information stored may include data, timing information, control data and other such information related to the tapped signals. The stored information may be provided to an external device for analysis.

Abstract: A method of managing a cell library regarding power optimization is disclosed. The method generally includes the steps of (A) reading a plurality of first modules within a first region of a circuit design stored in a design file, (B) calculating a first merit value indicating a relative sensitivity of the first region to a power consumption, the first merit value having a range from a static power dominated value to a dynamic power dominated value and (C) creating a constraint file configured to limit a design tool to a first subset of a plurality of replacement modules based on the first merit value such that the design tool automatically optimizes the power consumption of the first region by replacing at least one of the first modules with at least one of the replacement modules within the first subset, the replacement modules residing in a library file.

Abstract: A method and system for utilizing a simplified resist process model to perform optical and process corrections. More specifically, the present invention provides a fast and easy post exposure bake (PEB) effects calculation which can be used in connection with OPC. The model can be used to increase OPC modeling accuracy, by taking PEB effects into consideration, without incurring a large overhead increase due to PEB calculation cost. The method includes providing an image, calculating initial acid concentration and adding acid concentration contours to the image, calculating deprotection concentration and adding deprotection concentration contours to the image, determining latent image contour without diffusion, moving the latent image contour in a direction of lower deprotection concentration to provide the final latent image, performing OPC on the chemically amplified resist using edge movement based on the final latent image, and repeating the process to obtain convergence.

Abstract: A method and circuit for enhancing the performance in a serial ATA interface uses a standard ATA queue automation circuitry that handles all the transmit/receive frame information structure (FIS) operations for ATA queue commands without interrupting the higher-level software and associated hardware, firmware, and drivers. If the standard ATA queue automation circuitry and command queues are not provided, then every FIS operation will interrupt the higher layer application program. The standard ATA queuing automation circuit preprocesses higher layer commands to write into the task file registers before initiating the transport layer for an FIS transmission and provides information regarding the success or failure of a command. Commands to be executed and completion command queues are preferably used to improve the performance further.

Abstract: Methods and structure for improved design remediation for previously inexplicable damage to core circuits of an application circuit design caused by CDM ESD events. Features and aspects hereof note that such previously inexplicable damage to core circuits of an application circuit design is caused by inductive coupling between the non-core circuits and the core circuits of an application circuit design. Features and aspects hereof automatically alter an application circuit design to provide remediation by various techniques to reduce the magnitude of such inductive coupling and to thereby reduce susceptibility of the application circuit to damage from CDM ESD events. The modifications may be enforced as rules during initial design of the application circuit or as reconfiguration of a design in response to simulation to discover inappropriate coupling in the design.

Abstract: An SIP for performing a plurality of hard and soft functions comprises standard IC die and custom platforms mounted to a substrate. Die are identified for each standard hard function, such as memory, processing, I/O and other standard functions and one or more user-configurable base platforms are selected that, when configured, execute the custom soft functions. Optionally, the substrate is laminated to the die and the platforms are attached to the substrate. Testing is performed by defining the configured base platforms coupled to logic representing the die and their connections and performing placement and timing closure on the combination.

Abstract: The present invention provides a semiconductor storage device that requires no specialized circuit or the like for reading redundancy data from a redundancy region, and that is capable of freely changing the arrangement of the redundancy region in the memory array area. A semiconductor storage device of the present invention includes a memory array configured as shown below. The memory array includes a user region which is composed of given page units and where user data is stored, and a redundancy region which is composed of the same given page units and where redundancy data is stored. The area in the memory array can be used either as the user region or as the redundancy region.

Abstract: A layered test pattern for measuring registration and critical dimension (CD) for multi-layer semiconductor integrated circuits is disclosed. A first layer includes a first pattern having vertical and horizontal portions. A second layer is formed over the first layer and includes a second pattern having vertical and horizontal portions having nominal vertical and horizontal phase shifts with respect to the vertical and horizontal portions, respectively, of the first pattern. The vertical and horizontal portions include periodically repeating vertical lines and horizontal lines, respectively. The nominal phase shifts may be half of the period of the vertical and horizontal lines. A scatterometry tool measures the width of the lines and the phase shift of the first pattern relative to the second pattern. The width of the lines corresponds to CD, whereas the difference between the measured phase shift and the nominal phase shift indicates variation in registration.

Abstract: Methods and structures within a SAS domain for automated tuning performance of a coupled pair of transceivers. In one aspect hereof, control registers of a transmitting transceiver coupled to a receiving transceiver are adjusted to a plurality of distinct combinations of settings. For each distinct setting, a test pattern may be transmitted from the transmitting transceiver to the receiving transceiver. Status registers of the transmitting transceiver and of the receiving transceiver may be read to identify errors in the transmission. Identified errors are counted for each for distinct setting of the control registers to determine a preferred setting to best tune operation of the transceiver pair. The testing may be performed by any SAS initiator device or SAS expander acting as an initiator and may be performed on any coupled pair of transceiver in the SAS domain.

Abstract: A test system includes a built-in self-test (BIST) circuit and a stress applicator for use in analyzing a memory array. The stress applicator applies a selective set of stress factors to the memory array, such as temperature and voltage conditions. The BIST circuit executes a test routine on the memory array to detect the presence of any faulty memory address locations that may arise under the prevailing stress condition. A full testing cycle involves iterative repetition of the functions performed by the stress applicator and BIST circuit, with variations in the stress factors across the testing iterations. An accumulator cumulatively stores the fault information generated by the BIST circuit during each testing iteration. Following completion of the testing cycle, a repair operation is performed by a built-in self-repair (BISR) circuit to remap the faulty memory address locations indicated by the accumulator to redundant memory address locations.