Abstract: A data transmission buffer circuit is provided for buffering communication data, which is divided into a plurality of multiple-bit data frames that have a start and an end. The buffer circuit includes a first-in-first-out (FIFO) buffer and a frame counter. The FIFO buffer has a write port and a read port. The write port includes a data input, a write control input and an end-of-frame flag input, which indicates whether data on the data input includes the end of one of the data frames. The read port includes a data output, a read control input, and an end-of-frame flag output, which indicates whether data on the data output includes the end of one of the data frames. The frame counter is coupled to the write port and the read port and generates a frame count output that represents a number of the data frames stored in the FIFO buffer.

Abstract: A modem generally comprising an analog front end circuit, a hybrid circuit, and a variable impedance element. The hybrid circuit may be configured to couple the analog front end circuit to a transmission line. The variable impedance may be disposed within the analog front end circuit and connected to the hybrid circuit to trim an echo cancelling function of the hybrid circuit.

Abstract: An integrated circuit having circuit structures, including at least one of logic elements and memory elements. A core is disposed at an interior portion of the integrated circuit. The core contains core power contacts and core ground contacts for providing electrical power to the circuit structures during functional operation of the integrated circuit. A peripheral is disposed at an edge portion of the integrated circuit. The peripheral contains signal contacts for sending and receiving electrical signals between the circuit structures and external circuitry. The peripheral also has peripheral power contacts and peripheral ground contacts for providing electrical power to the circuit structures during testing of the integrated circuit. The peripheral power contacts are redundant to at least some of the core power contacts, and the peripheral ground contacts are redundant to at least some of the core power contacts.

Abstract: A signal amplitude comparator which includes a first differential input circuit that is biased, is configured to receive an input voltage and is configured to generate a first output current that is a non-linear function of the input voltage, a second differential input circuit which is biased similarly to the first differential input circuit, is configured to receive a reference input voltage and is configured to generate a second output current that generally tracks process, temperature and supply variation, and a comparator which is connected to the first differential input circuit and the second differential input circuit and is configured to receive the first output current from the first differential input circuit and the second output current from the second differential input circuit. The comparator is configured to compare the first and second output currents and generate an output which indicates whether the input voltage exceeds a pre-determined threshold value.

Abstract: An apparatus and method for protecting a probe card during a sort sequence are provided. With the apparatus and method, one or more probe card protectors are attached to a probe card. When the wafer is driven toward the probe card, if an amount of overdriving of the probe card occurs, the probe card protectors come into contact with the wafer. By pressing against the wafer, the probe card protectors generate a force that causes a driver motor of the driving mechanism to stall, thereby avoiding any further overdrive of the probe card and avoiding damage to the probe card.

Abstract: A method for generating constraint codes in a stream of data having a plurality of multi-bit source words, comprising the steps of (A) checking a sequence portion of the multi-bit source words for one or more constraint violations and (B) if no constraint violations are detected, modifying a predetermined portion of each of the multi-bit source words to generate a plurality of corresponding multi-bit code words configured to prevent the constraint violations of the sequence portions across an adjacent two of the multi-bit code words.

Abstract: A clock divider circuit and methods of operating same includes a standard integral clock divider circuit and a phase slip non-integral divider circuit for high granularity non-integral clock division. A multi-phase frequency synthesizer produces a plurality of phases of a clock frequency and applies the multiple phases to the divider circuit of the present invention. In a first embodiment, each phase is applied to a phase slip divider circuit which includes a integral divider portion and a programmable phase slip divider portion which receives the output of the integral division portion. Each phase of the input clock may therefore be divided by a wide variety of integral and non-integral divisors. In a second, simpler embodiment, a multi-phase frequency synthesizer produces a plurality of phases and applies the phases to a single phase slip divider.

Abstract: Provided is a technique for fabrication of STIs in a semiconductor device using implantation of damaging high-energy ions to insulating material overburden to generally and/or selectively increase insulation overburden removal rates. This technique avoids the use of chemical mechanical planarization (CMP) with a combination of implantation and, in some instances, low cost batch etching. The electrical characteristics of devices created with the new technique match closely to those fabricated with the standard CMP-based technique.

Abstract: A method for determining the signal constellation of a received signal establishes a moment based on each waveform, squares the moment, fourth powers the moment, divides the fourth power by the square to obtain a ratio, and compares the ratio to a threshold. If the ratio is less than threshold, the signal constellation corresponds to a first type, and if greater than the threshold, the signal constellation corresponds to a second type. The method can be generalized to a magnitude mean in place of a second moment.

Abstract: A netlist graph of an IC cell contains cell pin vertices, auxiliary vertices, and edges between vertices having a length. A clock shift SH(V) is assigned to each auxiliary vertex so that for any two auxiliary vertices, a difference between the clock shift of the two auxiliary vertices is no greater than a design time of the two auxiliary vertices. The clock shift is assigned such that SH(V1)+DELAY(V1,V2)−SH(V2)≦f·BOUND(V1,V2), where SH(V1) and SH(V2) are the clock shift of first and second auxiliary vertices, DELAY(V1,V2) is a maximal delay of the path between the first and second auxiliary vertices, f is a minimize constant, and BOUND(V1,V2) is a timing restriction of the first and second auxiliary vertices.

Abstract: A method for composing a dielectric layer within an interconnect structure of a multilayer semiconductor device is disclosed. A layer of silica precursor material is first deposited on a silicon substrate. Without affecting its structure and porosity, the layer of silica precursor material is then dried; and the layer of silica precursor material becomes porous silica film. Subsequently, a protective layer, such as parylene, is deposited on top of the dried porous silica film. The thickness of the protective layer should be greater than the peak-valley planarization requirements of the silicon substrate surface. As a result, a composite porous silica film, which services as a dielectric layer within an interconnect structure, is formed. This composite porous silica film has a relatively low dielectric constant and is able to withstand damage from a standard CMP procedure.

Abstract: A polyphase amplitude detector for detecting the amplitude of a polyphase signal. The polyphase amplitude detector includes means for generating differential pair signals. The differential pair signals are buffered and amplified and then AC coupled to the amplitude detector. The amplitude detector detects the amplitude of each phase of the polyphase signal and generates output signals which are used to control the amplitude of the polyphase signal.

Abstract: Methods and structure in a memory controller for sequencing memory device page activation commands to improve memory bandwidth utilization. In a synchronous memory device such as SDRAM or DDR SDRAM, an “activate” command precedes a corresponding “read” or “write” command to ensure that the page or row to be accessed by the “read” or “write” is available (“open”) for access. Latency periods between the activation of the page and the readiness ofthe page for the corresponding read or write command are heretofore filled withnop commands. The present invention looks ahead for subsequent read and write commands and inserts activation commands (hidden activates) in nop command periods of the SDRAM device to prepare a page in another bank for a read or write operation to follow. This sequencing of activate commands overlaps the required latency with current read or write burst operations.

Abstract: In an integrated circuit, a voltage level shifter transitions an input signal at a first voltage level to an output signal at a second voltage level. The voltage level shifter generally includes switching elements, such as transistors, that control switching the output signal between logical zero and logical one values. The switching elements have a maximum voltage below which they can operate. The maximum voltage is less than the second voltage level. The voltage across the switching elements is limited to less than the maximum voltage.

Abstract: A process is disclosed for forming an integrated circuit structure characterized by formation of a combined dielectric layer and antireflective coating layer. The process comprises forming a layer of dielectric material over an integrated circuit structure, and treating the surface of the layer of dielectric material to form an antireflective coating (ARC) surface therein. When a layer of photoresist is then formed over the ARC surface, and the layer of photoresist is exposed to a pattern of radiation, the ARC surface improves the accuracy of the replication, in the photoresist layer, of the pattern of radiation. Preferably, the surface of the dielectric layer is treated with a plasma comprising ions of elements and/or compounds to form the ARC surface.

Abstract: A positive photoresist bead is removed from an edge surface of a substrate by exposing the photoresist bead with light from an exposing source along a plurality of non-parallel paths approximately normal to the surface of the photoresist bead. The light may be simultaneously directed by a light guide along the non-parallel paths, or a mount may support the light guide adjacent the bead to move the light guide to various positions to direct the light along the non-parallel paths. Alternatively, plural light sources direct light to the bead along non-parallel paths. In any case, the exposed photoresist bead is then removed with a solvent.

Abstract: A method of forming a semiconductor on insulator structure in a monolithic semiconducting substrate with a bulk semiconductor structure. A first portion of a surface of the monolithic semiconducting substrate is recessed without effecting a second portion of the surface of the monolithic semiconducting substrate. An insulator precursor species is implanted beneath the surface of the recessed first portion of the monolithic semiconducting substrate, and a trench is etched around the implanted and recessed first portion of the monolithic semiconducting substrate. The insulator precursor species is activated to form an insulator layer beneath the surface of the recessed first portion of the monolithic semiconducting substrate. The semiconductor on insulator structure is formed in the first portion of the monolithic semiconducting substrate, and the bulk semiconductor structure is formed in the second portion of the monolithic semiconducting substrate.

Abstract: A method of forming a narrow isolation structure in a semiconducting substrate. The isolation structure is a trench that has a bottom and sidewalls, and that is to be filled with an isolating material. The isolating material has desired electrical properties and desired chemical properties, and is substantially reactively grown from the semiconducting substrate. A precursor material layer is formed on the bottom of the trench and on the sidewalls of the trench. The precursor material layer has electrical properties and chemical properties that are substantially similar to the desired electrical properties and the desired chemical properties of the isolating material. A substantial portion of the precursor material layer is removed from the bottom of the trench to expose the semiconducting substrate at the bottom of the trench, while leaving a substantial portion of the precursor material layer on the sidewalls of the trench.

Abstract: A method of determining a desired connection path between a pair of points of a net separated by one or more blockages, while reducing path delays and ramp time violations and without placing buffers within any of the blockages.

Abstract: An integrated inductor is formed on an integrated circuit or other substrate. The inductor is formed of a stack of almost totally enclosed rings of conductive material in which each ring has a single gap. Vias connect adjacent rings on opposite sides of their gaps so as to form a coil shaped structure. The inductor has applications in filtering, in an oscillator, in an antenna, combined with an active detection circuit, combined with an electron source, in a microelectromechanial systems or MEMS, or the like. The inductor may be formed in a vertical orientation or in a horizontal orientation. Chemical mechanical polishing may be used for planarizing layers.