Abstract: A microcomputer comprises a selecting unit for selecting one of a plurality of clock signals generated by a plurality of clock generating sources according to a selection instruction from a central processing unit or CPU, a clock generation stop unit, responsive to a stop instruction to stop generation of a clock signal other than the selected clock signal from the CPU, for causing a corresponding clock generating source to stop the generation of the clock signal, and an unauthorized stop process detecting unit, responsive to a stop instruction to stop the generation of the selected clock signal from the CPU, for determining that the CPU has provided an instruction to perform an unauthorized process of causing a selected clock generating source to stop the generation of the selected clock signal.

Abstract: Interconnectors are placed on a die containing a semiconductor device or integrated circuit which is to be tested or analyzed. The interconnector includes a bump contact for contacting a bond pad of the die, and a probe pad at a position spaced from the bump contact. An interconnector connects the bump contact and the probe pad. The interconnector is attached to the die with the bump contact in electrical contact with the bond pad and with the probe pad extending beyond an exterior peripheral edge of the die. Probes apply signals or power to the probe pad, and those signals and power are applied to the semiconductor device or integrated circuit to establish functionality for the test or analysis.

Abstract: A circuit and method are disclosed herein for a crystal oscillator, wherein the Q of the resonant network is not reduced through the loading effects of the oscillator's resistive bias network. The oscillator is configured as an operational transconductance amplifier (OTA) coupled to the resonant network. The OTA creates a negative resistance, which compensates for energy lost to resistance within the resonant network, thereby sustaining oscillation at the resonant frequency. Instead of using bias resistors to set and maintain the operating point of the oscillator, another OTA (with a high output impedance) injects a current into the resonant network to bias the oscillator. Advantageously, this technique avoids the reduction in Q that occurs when bias resistors are connected across the high effective parallel resistance of the resonant crystal. The higher Q benefits frequency stability and phase jitter characteristics of the oscillator.

Abstract: An electrically non conducting material disposed within one or more of the voids of a probe card between a substrate thereof and a tester interface to reinforce the substrate against flexing, bending, and warpage.

Abstract: A first-order digital PLL configured to accommodate a large frequency difference between a clock signal embedded in an incoming data stream received by a phase-locked loop and a local reference clock signal received by a phase-locked loop circuit. The PLL includes a data sampler which receives the incoming data stream, a frequency-locked loop (FLL) which receives the incoming data stream and is connected to the data sampler, and a frequency synthesizer which receives the local reference clock signal and is connected to the FLL. The FLL is provides a signal having a frequency which is substantially equal to the frequency of the local reference clock signal when no incoming data stream is received by the FLL, and provides a signal having a frequency which is substantially equal to the frequency of the incoming data stream when the FLL receives the incoming data stream.

Abstract: A method for fabricating a semiconducting device on a substrate, where the improvement includes forming a strained silicon germanium channel layer on the substrate. A gate insulation layer is formed on top of the strained silicon germanium channel layer, at a temperature that does not exceed about eight hundred centigrade. A gate electrode is formed on top of the gate insulation layer, and the gate electrode is patterned. A low dose drain dopant is impregnated into the substrate, and activated with a first laser anneal. A source-drain dopant is impregnated into the substrate, and activated with a second laser anneal. After the step of activating the low dose drain dopant with the first laser anneal, an insulating layer is formed around the gate electrode, at a temperature that does not exceed about eight hundred centigrade, and a spacer is formed around the gate electrode. The spacer is formed of a material that is reflective to the second laser anneal.

Abstract: An integrated circuit having a gate region, a source drain region, and an electrically nonconductive spacer separating the gate region and the source drain region. A local interconnect electrically connects the gate region to the source drain region across the electrically nonconductive spacer. The local interconnect is formed of a semiconducting material reacted with a metal. The local interconnect may be formed by implanting a precursor species into the electrically nonconductive spacer. A metal layer is deposited over at least the electrically nonconductive spacer, and the integrated circuit is heated to form an electrically conductive local interconnect from the metal layer and the precursor species implanted in the electrically nonconductive spacer.

Abstract: A method and circuit control a quiescent current of an amplifier including a preamplifier, error amplifiers, and output devices driven by the error amplifiers, the error amplifiers having an input-referred offset voltage. The method includes (a) applying a calibration voltage to an input of the error amplifiers, (b) calibrating a quiescent current of the output devices by changing the calibration voltage so that the calibrated quiescent current has a predetermined current value, the calibration voltage corresponding to the calibrated quiescent current being set as a correction voltage, and (c) operating the amplifier with the correction voltage applied to the input of the error amplifiers. The circuit includes a correction voltage generator supplying a correction voltage to the error amplifier input, a quiescent current detector detecting the quiescent current, and a calibration circuit adjusting the correction voltage so that the quiescent current is calibrated to a predetermined current value.

Abstract: An integrated circuit package includes a connector board and plural levels of individual conductors and conductive vias disposed through the connector board to form electrical connections between external connection pads on an undersurface of the connector board and finger connections on the upper surface of the connector board. An integrated circuit die is mounted in a central region of the connector board within confines of the individual conductors that are arranged about the die, and wire bond connections are formed between selected ones of the finger connections, the individual conductors, and the connection pads on the integrated circuit die to provide distributed connections for ground and power at one or more operating voltage levels on the individual conductors.

Abstract: A read data synchronization circuit for use in a Double Data Rate (DDR) memory system is provided. The read data synchronization circuit provides programmable timing signals for use in synchronizing read data.

Abstract: A package substrate having sides, which is formed of multiple non electrically conductive layers laminated together. Each of the multiple non electrically conductive layers is formed of a first lamina and a second lamina bonded together in a resin matrix. The first lamina is formed of woven fibers having a first warp. The first warp of the first lamina is disposed at a positive orientation of a first angle from the sides of the package substrate, where the first angle is neither zero degrees nor ninety degrees. The second lamina is also formed of woven fibers, having a second warp. The second warp of the second lamina is disposed at a negative orientation of the first angle from the sides of the package substrate. Electrically conductive layers are dispersed between different ones of the multiple non electrically conductive layers, with electrical connections dispersed between different ones of the electrically conductive layers.

Abstract: An apparatus comprising one or more first processors and one or more second processors. The one or more first processors may each comprise a first random access memory (RAM) sections. The one or more second processors may each comprise a read only memory (ROM) section and a second RAM section. The one or more first processors may be configured to operate in either (i) a first mode that executes code stored in the one or more ROM sections or (ii) a second mode that processes code stored in the one or more first RAM sections. The one or more second processors may be configured to execute code from either (i) the one or more ROM sections or (ii) the one or more second RAM sections. The apparatus may provide interoperability that may increase system observability and decrease system debugging complexity.

Abstract: Presented in this invention is a fabricating method and its array organization for a high-density twin MONOS memory device integrating a twin MONOS memory cell array and CMOS logic device circuit.

Abstract: A communications layer is provided between a host-based SCSI initiator and a SCSI target device to fully automate the validation process. The communications layer allows the host to direct variation and modification of the target parameters and behavior using vendor unique commands. The behavioral modification aims to establish interoperability by conforming the behavior of the target to the host behavior. The host-based initiator transports a suitable command structure to the target device containing appropriate ones of the vendor unique commands and associated parameter data. The target executes and otherwise processes the command structure to effectuate a reconfiguration according to the specifics of the command code. The command code is sufficient to fully reconfigure the SCSI target. Accordingly, the reconfiguration process is carried out in a fully automated fashion.

Abstract: A method of tracking information associated with an integrated circuit on a substrate after it has been diced. A set of parameters is collected during a first testing process. A first signature is determined for the integrated circuit, based on the set of parameters collected during the first testing process. The first signature and other information are associated with the integrated circuit. The integrated circuit is diced. The set of parameters is collected anew during a second testing process. A second signature is determined for the integrated circuit, based on the data set of parameters collected anew during the second testing process. The second signature is compared to multiple first signatures to locate the first signature that substantially matches the second signature. The other information associated with the first signature is associated with the diced integrated circuit.

Abstract: According to the present invention, a voltage level shifter with smaller size and less latch-up probability is described, in which extra two N-MOS transistors and two P-MOS transistors are added. The extra transistors help node voltages increase or decrease appropriately, and then the size of driving transistors can be small. As a result, the total size of the layout can be smaller. In addition, the voltage increasing or decreasing done by the extra transistors reduce a voltage bouncing which call cause latch-up.

Abstract: A method an apparatus are provided for calibrating a mask signal which is used for masking a data strobe signal that is received from a memory device with read data. According to the method, one or more read operations are performed with the memory device, and the data strobe signal is sampled at a plurality of different time delays relative to a local clock signal to produce a plurality of data strobe sample values. The plurality of data strobe sample values are searched to identify a temporal location within a preamble phase of the data strobe sample values and one of the time delays that corresponds to the temporal location. A delay at which the mask signal is disabled in response to a read operation is then set relative to the local clock signal based on the time delay corresponding to the temporal location.

Abstract: A method of characterizing worst case timing performance includes the steps of receiving as input a netlist of a core, performing a parasitic extraction on the netlist to generate a first standard parasitic extraction format file for a first assumed top metal layer over the core, performing a parasitic extraction on the netlist to generate a second standard parasitic extraction format file for a second assumed top metal layer over the core, calculating a minimum timing value from each delay arc of the first standard parasitic extraction format file, calculating a maximum timing value from each delay arc of the second standard parasitic extraction format file, and merging the minimum timing value calculated from each delay arc of the first standard parasitic extraction format file and the maximum timing value of each delay arc calculated from the second standard parasitic extraction format file to generate an output file.

Abstract: A method and system for splicing a first and a second compressed digital video bit stream, the first having a plurality of entry points, includes associating with each entry point an associated threshold buffer fullness such that if an actual video buffer verifier (vbv) fullness, just before removal of the bits of a first picture following the entry point equals or exceeds the associated threshold fullness, the portion of the first compressed digital bit stream following the entry point may be decoded without causing the vbv to underflow. Using an encoder, the second compressed digital video bit stream is generated. The second compressed digital video bit stream results in an ending fullness of a vbv one picture time after removal of the bits corresponding to a last picture of the second compressed digital video bit stream. This ending fullness equals or exceeds the threshold fullness associated with one of the entry points.

Abstract: A dual port enclosure monitor for servicing a dual port bus includes four primary components: two enclosure monitors and two bus expanders with isolation circuitry. The sub-system is configured such that an enclosure monitor and an expander are both connected to an external port. The internal bus then connects the two expanders, as well as all of the internal devices (e.g. hard drives, CD-ROMs, tape drives). The enclosure monitors can communicate with various host devices over the external buses. These host devices can instruct the enclosure monitor to either connect or isolate the internal bus, thereby the peripherals attached to it. This is accomplished through a set of independent control signals that run between the monitor and the expander. There are three different methods of control. The first is independent, paired control between enclosure monitor/bus expander pairs. A separate host controls each enclosure monitor/bus expander pair.