Abstract: To reduce FIFO access cycles across a system bus in a multi-processor system in which two processors communicate across a system bus through a FIFO, two separate FIFO descriptors are provided. The first descriptor is maintained by the processor located on-board with the FIFO, and the second descriptor is maintained by an off-board processor which communicates with the FIFO across the bus. When one processor performs a FIFO operation, the processor updates the other processor's descriptor via a memory access across the bus. Additionally, one module passes credits to the other to indicate that the latter has permission to perform a plurality of FIFO operations consecutively. In one embodiment a special non-valid data value is used to indicate an empty FIFO position.

Abstract: A method and composition for a composite spacer with low overlapped capacitance includes a low-k dielectric spacer layer. A first spacer is deposited on a partially formed semiconductor device having a gate oxide stack, followed by a low dielectric constant spacer layer. Anisotropic etching of the combined layers form spacers surrounding the gate oxide stack.

Abstract: A method of integrated circuit design and a circuit design tool. Critical paths are identified in an integrated circuit design. Identified edges are weighted. Edges are assigned a higher weight responsive to the number of critical paths in which they are included. A net criticality is assigned to each weighted edge based upon the edge's weight. Cells are re-placed and wired according to net criticality.

Abstract: A method of forming a narrow isolation structure in a semiconducting substrate. The isolation structure is a trench that has a bottom and sidewalls, and that is to be filled with an isolating material. The isolating material has desired electrical properties and desired chemical properties, and is substantially reactively grown from the semiconducting substrate. A precursor material layer is formed on the bottom of the trench and on the sidewalls of the trench. The precursor material layer has electrical properties and chemical properties that are substantially similar to the desired electrical properties and the desired chemical properties of the isolating material. A substantial portion of the precursor material layer is removed from the bottom of the trench to expose the semiconducting substrate at the bottom of the trench, while leaving a substantial portion of the precursor material layer on the sidewalls of the trench.

Abstract: An apparatus comprising a one or more memory circuits and an uncompress circuit. The one or more memory circuits may be configured to (a) store (i) a number of compressed code words and (ii) a number of delta words and (b) provide random access to the compressed code words in response to an address. The compressed code words may be losslessly compressed in response to (i) a number of uncompressed code words and (ii) the delta words. The delta words generally comprise bit strings that may be configured to minimize a size of the one or more memory circuits when deleted from the uncompressed code words. The uncompress circuit may be configured to losslessly uncompress the compressed code words in response to the delta words.

Abstract: A mask is designed for use in a photolithographic process to offset effects of light diffraction. At least one region having a length along each edge of a mask feature is defined. Error values at selected points on the mask are derived from an aerial image of the mask features and a target light intensity measured during IC fabrication process development. A matrix is derived representing the contributions of light amplitude due to movement of each region in a direction normal to the region. The amount of movement of each region is based on least-squares fitting the linear expressions in the matrix to the error values. The amount of movement may be adjusted for movement of an adjacent region.

Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

Abstract: A method of estimating the number of available transit connections of a hardmac includes the steps of calculating a total layer capacity of the hardmac; calculating a number of available transit connections from the total layer capacity; estimating a number of transit connections used for internal routing; calculating an absolute porosity of the hardmac from the number of available transit connections and the number of transit connections used for internal routing; calculating a relative porosity of the hardmac from the total metal layer capacity and the absolute porosity; and generating as output the relative porosity of the hardmac as an estimated porosity.

Abstract: A CPU outputs address data indicating a data storing unit or an OSD-RAM to access the data storing unit or the OSD-RAM, and an OSD logical circuit sometimes accesses the OSD-RAM to display data on an on-screen display. The address data is decoded in an OSD-RAM address decoder, and a decoded signal of “0” or “1” is output to an OR gate. Also, a value “0” normally set in a 1-wait register is output to the OR gate. When the address data indicates the data storing unit, a value “0” is output from the OR gate to a bus interface unit (BIU), an access mode of the CPU is set to a no-wait access mode corresponding to a shortest cycle, and the CPU accesses the data storing unit at the no-wait access mode.

Abstract: A capacitor and a capacitor dielectric material are fabricated by adjusting the amount of an ionic conductive species, such as hydrogen, contained in the capacitor dielectric material to obtain predetermined electrical or functional characteristics. Forming the capacitor dielectric material from silicon, nitrogen and hydrogen allows a stoichiometric ratio control of silicon to nitrogen to limit the amount of hydrogen. Forming the capacitor by dielectric material plasma enhanced chemical vapor deposition (PECVD) allows hydrogen bonds to be broken by ionic bombardment, so that stoichiometric control is achieved by controlling the power of the PECVD. Applying a predetermined number of thermal cycles of temperature elevation and temperature reduction also breaks the hydrogen bonds to control the amount of the hydrogen in the formed capacitor dielectric material.

Abstract: A method of control cell placement for an integrated circuit design includes the steps of receiving as input a description of a datapath structure for a hardmac; calculating a globally optimum placement with respect to connection length and delay for a group of control cells in the plurality of control cells; placing the plurality of control cells in at least one placement box; adding the placement of the plurality of control cells to an existing placement of a plurality of datapath cells in the description of the datapath structure to generate a globally optimum datapath structure for the plurality of control cells; and generating as output the globally optimum datapath structure.

Abstract: An on-chip decoupling capacitor cell is disclosed that is compatible with standard CMOS cells. A cell boundary defining the area of the cell includes a first transistor area and a second transistor area. A PMOS transistor having an n-well is formed within the first transistor area. The on-chip decoupling capacitor cell further includes an n-well extension that extends the n-well into the second transistor area, thereby providing a decoupling capacitor cell having reduced leakage compared to a CMOS capacitor cell, and increased capacitance per unit area compare with a traditional PMOS capacitor cell.

Abstract: A process is disclosed for planarizing a semiconductor substrate after filling isolation trenches in the substrate with dielectric material wherein the respective thicknesses of a liner layer of dielectric material blanket deposited over the upper surface of the substrate and in the trenches, and/or a filler layer of dielectric material blanket deposited over the liner layer to fill the trenches, may not be uniform.

Abstract: An integrated circuit package is provided that allows high density routing of signal lines. A substrate of the package may include an upper surface upon which a bonding finger resides, a lower surface upon which a solder ball resides, and a signal conductor plane on which a signal trace conductor resides a dielectrically spaced distance between the upper surface and the lower surface. A first via may extend perpendicularly from the upper surface, connecting the bonding finger to the first portion of the signal trace conductor. A second via may extend perpendicularly from the lower surface, connecting the solder ball to the second portion of the signal trace conductor. The routing of the vias and signal trace conductors may cause the signal lines to either fan into or away from the area of the integrated circuit package adapted to receive the integrated circuit.

Abstract: A method for storing data in a solid state device, comprising the steps of (A) retrieving data from a source device, (B) storing said data in a compressed format to said solid state device and (C) accessing and uncompressing portions of said data from said solid state device, wherein said portions represent data to be executed in response to an address.

Abstract: An apparatus generally having a threshold slicer, a state logic device and a converter. The threshold slicer may be configured to generate a (i) first signal having an initial state of a plurality of states in response to a preceding value and a present value from an input signal and (ii) a second signal having a plurality of levels in response to the preceding value and the present value. The state logic device may be configured to generate a third signal having a sequence of the plurality of states starting with the initial state in response to the first signal. The converter may be configured to generate an output signal having the plurality of levels in response to the plurality of states in the third signal.

Abstract: Provided is a method and apparatus for pseudo-random noise (PN) code sequence hopping by storing a base state of a PN code sequence generator that generates a PN code sequence and by identifying a number of states to advance the PN code sequence, the number being greater than one. A transformation function is then obtained based on the number of states to advance the PN code sequence. The PN code sequence is advanced by the identified number of states from the base state to obtain a new state, by utilizing the transformation function. Finally, the new state is loaded into the PN code sequence generator and the PN code sequence generator is enabled with the new state.

Abstract: A method of forming junctions in a semiconductor substrate, where a gate dielectric layer is grown on the semiconductor substrate, a gate electrode layer is deposited on the gate dielectric layer, and a sacrificial layer is formed on the gate electrode layer. The sacrificial layer is patterned with a material to cover portions of the sacrificial layer and expose portions of the sacrificial layer. The exposed portions of the sacrificial layer are etched to remove the exposed portions of the sacrificial layer and expose portions of the gate electrode layer. The exposed portions of the gate electrode layer are etched to expose portions of the gate dielectric layer and form a gate electrode having exposed vertical faces. The sacrificial layer and the exposed portions of the gate dielectric layer are impregnated with a first species that inhibits diffusion of oxygen through the sacrificial layer and the exposed portions of the gate dielectric layer.

Abstract: A data structure contains sequence number metadata which identifies an input/output (I/O) operation such as a full stripe write on a redundant array of independent disks (RAID) mass storage system, and also contains revision number metadata which identifies a subsequent I/O operation such as a read modify write on only a fractional component of the entire user data. The sequence number and revision number metadata are used in an error detection and correction technique, along with parity metadata, to detect and correct silent errors arising from inadvertent data path and drive data corruption. An error to a portion of the stripe is detected by a difference in sequence numbers for all of the components of data. An error arising after an I/O operation is detected by a revision number which is different from the correct revision number.

Abstract: A method and apparatus are provided for recycling power in an integrated circuit. The integrated circuit includes a plurality of nets and a switched capacitor network. The plurality of nets includes a first logic net having a tendency to repetitively switch between logic high and low states during normal operation of the integrated circuit. The switched capacitor network includes a plurality of capacitors, which are selectively decoupled from the plurality of nets, selectively coupled to the first logic net in parallel with one another, and selectively coupled to at least one of the nets in series with one another.