Abstract: An interposer card used during qualification tests on integrated circuit packages is disclosed that eliminates the need for sockets and custom boards. The interposer card includes pads for mounting the I/Os of a test package; edge card connectors for connecting the interposer card directly to a test board and for performing bias testing on the test package; and pads for replicating the test package I/Os for connecting the interposer card to an automated electrical testing (ATE) system for performing ATE tests on the test package.

Abstract: A process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section therein. A capacitor dielectric layer is formed adjacent the upper layer. The capacitor dielectric layer covers the first capacitor electrode section. A second capacitor electrode layer is formed adjacent the capacitor dielectric layer. The second capacitor electrode layer includes a second capacitor electrode section that at least partially covers the first capacitor electrode section, and which has an edge portion that extends beyond the underlying first capacitor electrode section. The capacitor dielectric layer being disposed between the first capacitor electrode section and the second capacitor electrode section. An upper dielectric layer is formed adjacent the second capacitor electrode section.

Abstract: A method for testing integrated circuits having associated position designations, where a predetermined set of input vectors is introduced as test input into the integrated circuits. The output from the integrated circuits in response to the predetermined set of input vectors is sensed, and the output from the integrated circuits is recorded in a wafer map, referenced by the position designations. The output from at least a subset of the integrated circuits is selected and mathematically manipulated to produce a reference value. The output for each of the integrated circuits in the selected subset is individually compared to the reference value, and graded integrated circuits within the selected subset that have output that differs from the reference value by more than a given amount are identified. A classification is assigned to the graded integrated circuits and recorded in the wafer map, referenced by the position designations for the graded integrated circuits.

Abstract: An oscillator provides output signals over a range of oscillating frequencies includes an resonant circuit, at least one active circuit device operatively coupled to the resonant circuit to supply energy to the resonant circuit, and at least one unidirectional device coupled to the active circuit device. The unidirectional device permits current to flow between the active circuit device and the resonant circuit when the active circuit device adds energy to the resonant circuit, and impedes a drain of energy from the resonant circuit due to increased output signal amplitude.

Abstract: In a storage system, such as a storage area network, a snapshot volume or one or more checkpoint volumes are formed from the same base volume using a single repository containing multiple images of data stored in the base volume. The first image is started with the formation of the snapshot volume or the first checkpoint volume and is filled with blocks of data copied from the base volume, thereby increasing in size within the repository, until the first image is stopped and the next image is started. The next image is then filled with blocks of data copied from the base volume until stopped. Thus, the blocks of data are copied only into the most recently created image within the repository. With the creation of each checkpoint volume, a new image is concurrently started in the same repository. Each checkpoint volume is dependent on the image that was created concurrently plus any images created thereafter.

Abstract: A system and method are presented for a write buffer that combines capabilities and features implemented in separate, specialized buffers in prior art microprocessors. The write buffer receives data records from a CPU and subsequently transfers them to a memory bus. In addition to the data records themselves, each location in the buffer contains a complement of control bits, which determine the mode in which the associated record will be transferred to the memory bus. The use of these bits allows the buffer to perform memory transfers associated with a write-back data cache or an EJTAG test module, as well as more conventional transfers traditionally performed by a write buffer. The combination of these multiple capabilities in a single write buffer is believed to simplify the design of the bus interface unit in a microprocessor incorporating the principles disclosed herein.

Abstract: A method for synchronizing clock pulses for an integrated circuit includes the steps of (a) finding a relative delay with respect to a clock signal for a plurality of circuit elements and (b) inserting a delay cell between the clock signal and each of the plurality of circuit elements for each of the plurality of circuit elements wherein the delay cell has a relative delay greater than a minimum delay to minimize clock skew.

Abstract: A programmable delay feature useful to reduce contention related delays between a memory controller device and a plurality of master devices sharing access to a memory subsystem through the single memory controller device. The programmable delay line is programmed to an optimal delay value for each master device prior to returning data to the requesting master device. A configuration register associated with the memory controller stores the optimal value for the delay line for the present application of the controller. Firmware operable on a processor coupled to the memory controller (or other programmable master device) may determine the optimal delay line value for the system. The optimal delay line value so determined is then stored in the memory controller's configuration register.

Abstract: A system, method and program for hierarchically designing integrated circuits(ICs). Potential sources of crosstalk are identified in the hierachical design and prior to and during placement and wiring while maintaining the hierachical structure. Blocks are placed and analyzed to determine if all blocks are well behaved and where necessary selectively re-organized to be well behaved. Blockages are inserted blocks to restrict top level wiring to avoid crosstalk. Orthogonal restrictions are placed on top level wiring as well as on top level wire lengths.

Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

Abstract: A method for allowing I/O requests to run concurrently during a rollback process, comprising the steps of (A) reading from and writing to an original volume and (B) running said I/O requests concurrently with the rollback process from a snapshot volume.

Abstract: An integrated circuit structure and a method for packaging an integrated circuit are described. The integrated structure includes an integrated circuit that is inverted and solder bump mounted to a substrate. An underfill is used to encapsulate the solder bumps and form a rigid support layer between the integrated circuit and the substrate. A heatspreader, which has larger planar dimensions than the integrated circuit, is centrally attached to an upper surface of the integrated circuit with a thermally conductive material. Lateral portions of the heatspreader extending beyond the edges of the integrated circuit are attached to the substrate and sides of the integrated circuit by a thermally conductive underfill material. The thermally conductive underfill material thus employed, among other things, provides a robust mechanical support to the heatspreader and integrated circuit structure and eliminates the need for additional support structures such as conventional stiffener rings.

Abstract: A reply descriptor for transmission over an I/O message passing medium in response to a corresponding request message, the descriptor comprises at least one indication field that can function as a ‘flag’ to identify its type, and a content field; whereby a reply message is generated only if at least one predefined condition is not met and the content field will, accordingly, comprise information of that reply message's storage location. The content field to comprise data copied from the I/O request message if each predefined condition is met. A method of responding over an I/O message passing medium to a request message comprising the steps of: generating a reply message to the request message only if at least one predefined condition is not met; generating a reply descriptor having at least one indication field and a content field; whereby the content field comprises information of the reply message's storage location if so generated.

Abstract: A client machine (12) is connected to a network medium (20) for use in managing the operation of a plurality of subsystems (14-18) that are also coupled to the network medium (20). The client machine (12) includes a cache memory (26) for storing management-related objects that have been retrieved by the client machine (12) from the individual subsystems (14-18). When called upon to manage a particular subsystem, the client machine (12) first determines which management related objects will be required to manage the subsystem. The client machine (12) then checks the cache memory (26) to determine whether any of the required objects are located therein before requesting the objects from the associated subsystem. In this manner, only objects that are not available locally are requested from the subsystem, thereby reducing management-related information traffic in the network (10).

Abstract: Cell terminals in an integrated circuit is interconnected by using multiple layers of conductors that are routed both orthogonally and non-orthogonally to each other. Non-orthogonally routed conductors have slopes that are ratios of non-zero integers which approximate ceratin predetermined angles. The integers in the ratios are chosen from integers generated by sequence equations. The conductors are routed by following grid lines in a grid system comprising both orthogonal grid lines and non-orthogonal grid lines having slopes generated by the sequence equations. Ratios of integers are used to approximate certain angles so that the conductors would intersect the cell terminals located on the fundamental grid intersection points. The conductors in different metal layers form different angles with other conductors in other metal layers based on the slopes of the conductors.

Abstract: A charged particle imaging system may be used to perform package-level failure analysis by providing a Capacitive Coupling Voltage Contrast image of a portion of the semiconductor package. Preliminary failure analysis using Time Domain Reflectometry may determine whether a defect lies either outside or within the semiconductor package substrate. The semiconductor package may be prepared such that sequential layers of the package may be removed until electrical testing determines the location of a defect on a layer of the package. An alternating signal may be supplied to an exposed trace conductor on the layer of the package substrate on which the defect is located. A portion of the trace conductor may be imaged with a charged particle imaging system to produce a voltage-induced contrast image of the trace conductors.

Abstract: A controller for a memory partitioned into a plurality of banks and divided into addresses that are accessed by a plurality of row access strobe signals and a plurality of column access strobe signals. The controller generally comprising a queue state machine, a plurality of transaction state machines and an arbitor. The queue snare machine may be configured to allocate a plurality of memory commands received by the controller among a plurality transaction state machines. A first of the transaction state machines may be configured to issue a first strobe request to assert one among the row access strobe signals and the column access strobe signals in response to receiving a first of the memory commands. A second of the transaction state machines may be configured to issue a second strobe request to assert one among the row access strobe signals and the column access strobe signals in response to receiving a second of the memory commands.

Abstract: A method for making a bump and trace layout for an integrated circuit die includes the step of replicating a routing tile having a first column of I/O pads and a second column of I/O pads wherein the first column is offset from the second column so that the I/O pads of the first column are interleaved between the I/O pads of the second column.

Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.