Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

Abstract: A method for programming a circuit comprising the steps of (A) simulating one or more states, (B) building program information in response to said simulation and (C) extracting from said simulation one or more unique states having current state to next state sequences. The present invention includes a method and/or architecture that may implement (i) content addressable memory system (CAMS), (ii) memory, (iii) register files and (iv) other logic to implement programmability on application specific integrated circuits (ASICs). The architecture is performance and cost competitive with field programmable gate arrays (FPGAs) and programmable logic devices (PLDs).

Abstract: A method of modeling delays in an integrated circuit design is disclosed that may be used to reduce the computation time of path delays in an integrated circuit design. A method of modeling delays in an integrated circuit design includes the steps of receiving as input a description of an integrated circuit design; identifying at least one small net in the integrated circuit design from the description; approximating an effective capacitance of the at least one small net by the total capacitance; and approximating an interconnect delay of the at least one small net by zero.

Abstract: A method for restoring an eroded portion in an exposed upper surface cavity of a metallic element in a microelectronic device, where the metallic element has a hardness, and the metallic element is laterally surrounded by lateral elements, where at least one structure within the lateral elements has a hardness that is greater than the hardness of the metallic element. A precursor material is deposited in at least the cavity of the upper surface of the metallic element. The precursor material is deposited to a thickness that at least fills the cavity of the upper surface of the metallic element. The precursor material has a hardness that is less than the hardness of the at least one structure within the lateral elements. The precursor material is removed as necessary from the lateral elements, and the precursor material is planarized. Only the precursor material within the cavity of the upper surface of the metallic element is selectively replaced with a desired material.

Abstract: The present invention is a method and apparatus for optimizing the design of a combinational circuit. The method includes constructing a circuit sheaf for the combinational circuit and then performing vector optimization with domination. In the preferred embodiment, a complete BDD B is determined and, from that, a list of F-sets is computed. If the combinational circuit includes cells other than NOT, AND and XOR cells, the circuit is first transformed such that it only has those types of cells.

Abstract: A memory cell having a transistor and a capacitor formed in a silicon substrate. The capacitor is formed with a lower electrically conductive plate etched in a projected surface area of the silicon substrate. The lower electrically conductive plate has at least one cross section in the shape of a vee, where the sides of the vee are disposed at an angle of about fifty-five degrees from a top surface of the silicon substrate. The surface area of the lower electrically conductive plate is about seventy-three percent larger than the projected surface area of the silicon substrate in which the lower electrically conductive plate is etched. A capacitor dielectric layer is formed of a first deposited dielectric layer, which is disposed adjacent the lower electrically conductive plate. A top electrically conductive plate is disposed adjacent the capacitor dielectric layer and opposite the lower electrically conductive plate.

Abstract: A digital system in a first clock domain synchronously initializes a logic circuit having a memory characteristic. The digital system includes first and second logic circuits. The first circuit includes an asynchronous port for receiving a reset signal from a second clock domain, a port for receiving a first clock signal for the first clock domain, and an output port for providing an initialization signal. The first circuit sets the initialization signal at a first logic value in response to the reset signal and maintains the first logic value at least until the first clock signal becomes active. The second circuit includes a synchronous port for receiving the initialization signal, a port for receiving the first clock signal, and a data output port outputting a data signal. The second circuit is initialized in response to the active first clock signal when the initialization signal has the first logic value.

Abstract: In order to reduce memory requirements in a chip for demodulating digital video broadcast signals, symbol data values stored for a channel equalisation process have their scattered pilots removed, to achieve a 9% reduction in memory space required. This is achieved by providing a write pointer and a read pointer, the write pointer being arranged to exclude carriers carrying scattered pilots, and the read pointer being arranged to read the stored symbol data, but to add nominal data values at positions of excluded scattered pilots.

Abstract: The present invention describes a multi-stage decoder and method of decoding utilizing a pseudo NAND or pseudo AND gate in one of the stages. This invention presents a decoder comprising a first stage circuit having two or more first inputs which generates one or more first outputs; and a second stage circuit having at least one second input and at least one second output, wherein the one or more first outputs are the same as the at least one second input, wherein at least one of the group consisting of the first stage circuit and the second stage circuit includes either a pseudo AND gate or a pseudo NAND gate. This invention presents a method of decoding, comprising the steps of generating a signal responsive to two or more address bits and enabling a decoder by the generated signal.

Abstract: A fade circuit adjusts the luma as well as one or more chroma components of a main video so that the fade ins and fade outs of the main video do not change the color of an on-screen display image, such as the volume bar. In one embodiment, luma component (Y) is adjusted by subtracting a fade factor from the luma component to form a faded luma component. At the same time, one or more chroma components (Cb and Cr) are scaled by (1) subtracting a predetermined value from the chroma component to form a resultant, (2) multiplying the resultant with a scale factor to form a product, and (3) adding the predetermined value to the product to form a faded chroma component.

Abstract: A memory controller includes a pair of input command decoders and a pair of multiplexers. If the memory controller receives a data transfer request related to a read or write burst which will stay within a page of memory, the first input command decoder circuit generates a first input command which is then passed, in sequence, by the first and second multiplexers. Conversely, if the data transfer request relates to a read or write burst which will burst over a page of the memory, the second input command decoder circuit generates second and third input commands. The second input command passes through the second multiplexer circuit while the third input command is held in a command register. The third input command is subsequently passed through the first and second multiplexers.

Abstract: A shallow isolating trench is formed in a semiconductor wafer between active component areas to electrically isolate the active components from each other. The isolating trench is primarily formed of an insulating material, such as an oxide, in a recess formed into the wafer. An etch resistant material, such as BTBAS nitride, is placed over the insulating material in the recess. The etch resistant material protects the insulating material from erosion due to subsequent semiconductor fabrication process steps, so the integrity of the isolating trench and the planarity of the wafer are generally maintained.

Abstract: A high Q tank circuit is employed at the output of a digital, crystal controlled oscillator to generate a high voltage amplitude signal. The tank circuit has a resonant frequency greater than the maximum required oscillation frequency. During each oscillation cycle, oscillation within the tank circuit is stopped in an energy efficient manner such that the resonant oscillation period is extended to match the required oscillation period. Modulation of the digital oscillator signal appears in the output circuit signal.

Abstract: An improved metal stack strategy is disclosed. A first aspect of the present invention provides a method for defining an optimized metal stack option based on critical path information. The method and system use interconnect data from timing critical paths from at least one previous design to generate interconnect statistical data. The interconnect statistical data is then used to vary physical properties of interconnects in a current design during simulation until optimum performance is achieved. A second aspect of the present invention provides a method for reusing an ASIC core design with different metal stack options. This method defines x common metal layers across at least two metal stack options, where interconnects on each of the metal layers have common physical and electrical characteristics. An ASIC core design based on the x common metal layers is also defined, thereby making the ASIC core compatible with the different metal stack options.

Abstract: A method and apparatus for manufacturing an electrostatic discharge protection device. A first gate structure for the electrostatic device is formed. A first lightly doped drain and a second lightly doped drain for the electrostatic discharge protection device is formed. A second gate structure for a data path transistor is formed. A third lightly doped drain and a fourth lightly doped drain for a data path transistor is formed, wherein the first lightly doped drain and the second lightly doped drain have a higher doping level relative to the third lightly doped drain and the fourth lightly doped drain.

Abstract: An apparatus comprising a first calibration circuit and a phase shift network stage. The first calibration circuit may be configured to generate a control signal. The phase shift network stage may comprise one or more tunable phase shift elements and be configured to provide a tunable impedance. The phase shift network stage may be tuned in response to the control signal and a conductance of the tunable phase shift elements.

Abstract: A package comprises a top die and a bottom die. The top die has top and bottom surfaces while the bottom die has top and bottom surfaces. The bottom die is mounted on a substrate, which has a top surface, such that the bottom surface of the bottom die faces the top surface of the substrate. The bottom surface of the top die is separated from the top surface of the bottom die by an interposer, which creates a space between the exterior regions of the top surface of the bottom die and the bottom surface of the top die. Each of a plurality of wires, which are electrically connected to the bottom die, runs through this space (i.e. runs between the top surface of the bottom die and the bottom surface of the top die), thereby permitting (if desired) the top die to be at least as large as the bottom die.

Abstract: A circuit which provides that a source voltage and a pad voltage are band-limited and source-followed down in order to get them into the input range of a comparator, the output of which signals an over-voltage condition on the pad. The circuit provides the ability to provide the relationship between the source voltage and pad voltage to a comparator with a very small, tightly-controlled offset. This translates to the ability to detect very small over-voltage conditions on an IO. The circuit consumes little power, is highly accurate, and requires no special, expensive process options. The circuit can be used anywhere there is a desire to compare (with a small, accurate offset) two signals that are close to a source voltage, such as VDD. The circuit can also be used to compare signals close to VSS.