Abstract: A method for blocking formation of a reacted metal layer on a structure in an integrated circuit. The integrated circuit has a source region, a drain region, a gate, an isolation area formed of a material, and a protective layer formed of substantially the same material as the isolation area. The protective layer overlies at least the source region and the drain region. The method is accomplished while reducing an amount of the material of the isolation area that is removed when the material of the protective layer is removed. A blocking layer is deposited on the integrated circuit. The blocking layer is formed of a material that is substantially different from the material of the isolation area and the protective layer. The blocking layer is patterned to selectively cover portions of the blocking layers that overlie at least the structure and selectively expose portions of the blocking layer that overlie at least the source region, the drain region, and the gate.

Abstract: A method is provided for programming data for a memory element of a twin memory cell (i). The word line WL1 is set to a programming word line selection voltage, the control gate CG[i+1] is set to a programming control gate voltage, and the control gate CG[i] is set to an over-ride voltage. The bit line BL[i+1] is set to a programming bit line voltage, and the bit line BL[i+2] is set to Vdd, but not to 0 V.

Abstract: A method is provided for programming data for a memory element of a twin memory cell (i). The word line WL1 is set to a programming word line selection voltage, the control gate CG[i+1] is set to a programming control gate voltage, the control gate CG[i] is set to an over-ride voltage, the bit line BL[i+1] is set to a programming bit line voltage, and the bit line BL[i] is connected to the constant current source.

Abstract: A circuit which provides that a source voltage and a pad voltage are band-limited and source-followed down in order to get them into the input range of a comparator, the output of which signals an over-voltage condition on the pad. The circuit provides the ability to provide the relationship between the source voltage and pad voltage to a comparator with a very small, tightly-controlled offset. This translates to the ability to detect very small over-voltage conditions on an IO. The circuit consumes little power, is highly accurate, and requires no special, expensive process options. The circuit can be used anywhere there is a desire to compare (with a small, accurate offset) two signals that are close to a source voltage, such as VDD. The circuit can also be used to compare signals close to VSS.

Abstract: An improved PCI verification method and apparatus provides iterative testing of all desired conditions or protocol combinations in a PCI system. One or more commands may be tested in combination with one or more functional behavior parameters throughout a desired range of variable parameter values. In one aspect, an apparatus and method for testing a PCI device for compliance under the PCI specification in target operation is provided. In another aspect, an apparatus and method for testing a PCI device for compliance under the PCI specification in master operation is provided.

Abstract: A method of control cell placement that is optimum for an area constraint of a datapath structure is disclosed that includes the steps of receiving as input a description of a datapath structure including a group of constrained control cells and an area constraint; calculating the optimum placement of the control cells that lie outside the area constraint; calculating an optimum placement of the control cells that lie inside the area constraint; and generating as output the optimum placement of the control cells.

Abstract: An adaptive equalizer for use in a communication receiver that prevents equalizer operation divergence in response to slicer errors in a high noise communication application. The equalizer uses the difference between an equalized sample value and the nearest constellation point determined by the slicer both as the equalizer adaptation value and as a control value to selectively enable or minimize (disable) adaptation modifications. The difference is compared to a threshold value to determine whether the difference should be applied to the equalizer for adaptation purposes or a minimal value to prevent equalizer divergence in response to significant slicer errors. The threshold value is determined as a function of the ratio of the probability of correct slicer determinations and the probability of incorrect slicer determinations for a given sample value and a given signal to noise ratio.

Abstract: A method and apparatus for arbitrating access to a memory, which has a plurality of banks. The method includes arbitrating with a plurality of processors. Each processor is associated with one of a plurality of data ports and has a plurality of arbitration cycles, including a current cycle and a most recent cycle preceding the current cycle. Each processor receives memory access requests from all of the data ports, wherein each memory access request is associated with one of the memory banks. Each processor selectively grants the data port associated with that processor access to the memory for the current cycle based on the banks associated with the memory access requests of each data port, the data port that was granted access to the memory during the preceding cycle, and the memory bank that was accessed during the preceding cycle.

Abstract: The present invention concerns an apparatus comprising a fixture and a sputtering device. The fixture may be configured to position a semiconductor wafer in a plasma. The sputtering device may be configured to sputter metal atoms onto a surface of the wafer in a direction perpendicular to the surface.

Abstract: A process for forming a low k carbon-doped silicon oxide dielectric material (lkc-dsodm) on an integrated circuit structure is characterized by improved planarity and good gap fill in high aspect ratio regions of the integrated circuit structure, as well as improved film strength and adherence, and less byproducts trapped in the film. The process comprises: depositing a plurality of layers of lkc-dsodm on an integrated circuit structure in a reactor; and pausing after depositing each layer of lkc-dsodm and before depositing a further layer of lkc-dsodm. The process can further include first forming a base or barrier layer of a silicon-rich and nitrogen-rich dielectric material over the integrated circuit structure, plasma etching the upper surface of the barrier layer to facilitate adhesion of the subsequently deposited lkc-dsodm to the barrier layer, and then, before depositing the first layer of lkc-dsodm, cooling the etched barrier layer down to within 10° C.

Abstract: A system and method for dynamically expanding a snapshot repository based on predefined parameters is disclosed. The snapshot repository is monitored for determining if the amount of information stored in the snapshot repository has reached a predetermined volume increase threshold. If a determination is made that the volume increase threshold has been reached, the volume of the snapshot repository is automatically increased. The snapshot repository may also be monitored for determining if the amount of information stored in the snapshot repository has reached a predetermined maximum snapshot repository volume whereupon a warning may be provided.

Abstract: A circuit that may comprise a data-cache memory and a data-path circuit. The data-cache memory may be configured to (i) store a cache input data item among a plurality of associative sets and (ii) present a plurality of cache output data items. The data-path circuit may be configured to (i) independently shift each of the plurality of cache output data items and (ii) multiplex the plurality of shifted cache output data items to present an output data item.

Abstract: A method of configuring a plurality of managed devices. The method preferably includes selecting a source managed device, obtaining a source configuration description from the source managed device, selecting one or more destination managed devices to be configured, issuing a configuration change command to each of the selected destination managed devices and applying the source configuration description selected from the source managed device to each of the selected destination managed devices. In addition, the method may further include the step of editing the source configuration description before issuing the configuration change commands to the one or more destination managed devices.

Abstract: A method of forming a localized oxidation having reduced bird's beak encroachment in a semiconductor device by providing an opening in the silicon substrate that has sloped sidewalls with a taper between about 10° and about 75° as measured from the vertical axis of the recess opening and then growing field oxide within the tapered recess opening for forming the localized oxidation.

Abstract: A method of applying a layer of material to a substrate. The substrate is received with a chuck, and the material is dispensed. The substrate is spun on the chuck, spreading the material and conveying a surplus of the material away. The surplus of the material conveyed away is entrained into an exhaust stream. A pressure drop is created in the exhaust stream across a vane anemometer. The blow back of the entrained surplus of the material from a downstream position in the exhaust system to the substrate is thereby reduced.

Abstract: A sign frame assembly for supporting a flexible fascia. In one embodiment, a frame member extends in a first direction and has first and second bracket-mounting sections spaced apart from each other in the first direction. First and second brackets have inner and outer opposite ends. The inner end of the first bracket is attached to the first bracket-mounting section of the first frame member. The inner end of the second bracket are pivotally mounted to the second bracket-mounting section of the frame member. First and second elongated fascia attachment members are affixed respectively to the outer ends of the first and second brackets. A flexible fascia having oppositely disposed edges is connected to the first and second elongated members.

Abstract: An electrically programmable read only memory device which has efficiency of electron injection from channel to floating gate is provided. This memory cell includes a control gate and floating gate between source and drain regions. The region under the floating gate has extremely small enhanced mode channel and N region. Therefore, this channel is completely depleted by the program drain voltage. The enhanced mode channel region is precisely defined by the side wall spacer technique. Also, the N drain region is accurately defined by the difference of side wall polysilicon gate and the first spacer.

Abstract: A method for simulating verification of an IC design. The method generally comprises the steps of (A) generating one or more transactions of a simulation and (B) testing the one or more transactions and possibly generating an exception. The exception may be configured to initiate a modification of step (A).

Abstract: A carbon-doped hard mask includes a dielectric material containing carbon which is released from the hard mask during a metal etching process. The released carbon is deposited on and bonds to sidewalls of the metal structure during the metal etching process to passivate the sidewalls of the metal structure and prevent lateral etching of the sidewalls during the metal etching process. The released carbon also prevents accumulation of metal residue in open fields.

Abstract: A method for forming the electrical interconnect levels and circuit elements of an integrated circuit is provided by the present invention. The method utilizes a relatively thin layer of conductive material having a higher resistance than the metal typically used to form electrical interconnections, such as titanium nitride, to provide relatively short local interconnections between circuit elements of the integrated circuit. In addition, this same thin layer of conductive material is used to form macro elements such as capacitors, resistors, and fuses in the integrated circuit. By allowing the removal of space consuming transverse electrical interconnect lines from the interconnect levels, the present invention increases the routing density of the electrical interconnect levels.