Abstract: A subprefix is selected from a prefix search tree that has a longest match to a search prefix. A binary search prefix is input to the root vertex of the tree, and is compared to the prefixes in selected hierarchy vertices. A bit is set in a search mask based on a least significant bit of a bit string in the search prefix that matches a longest bit string in a prefix in each vertex. A longest matching subprefix is selected from a string of most significant bits of the search prefix based on the lowest significant bit set in the search mask. A prefix mask is also provided for each prefix in the tree, and is useful in connection with construction of the search mask.

Abstract: Silicon nitride gate insulators for digital transistors and silicon dioxide gate insulators for analog transistors of a hybrid integrated circuit (IC) are formed in a single integrated fabrication process. A first area of a silicon substrate of the IC is exposed while a second area is initially covered by a silicon dioxide layer. A layer of silicon nitride is formed on the exposed first area while the initial silicon dioxide layer inhibits the formation of silicon nitride on the second area. Thereafter the initial silicon dioxide layer is removed from the second area to allow a new silicon dioxide layer to be formed there from the exposed silicon substrate. The silicon dioxide layer shields against the adverse influences from silicon nitride formation and permits the initial silicon dioxide layer to be removed by etching. The silicon nitride layer shields against the adverse influences of oxidizing new silicon dioxide layer.

Abstract: An apparatus for performing contaminant sensitive processing on a substrate. A substrate load chamber receives the substrate from an ambient contaminant laden environment, and isolates the substrate from the ambient contaminant laden environment. The substrate load chamber further forms a first environment of intermediate cleanliness around the substrate. A substrate pass through chamber receives the substrate from the substrate load chamber, and isolates the substrate from the intermediate cleanliness of the first environment of the substrate load chamber. The substrate pass through chamber further forms a second environment of high cleanliness around the substrate. A substrate transfer chamber receives the substrate from the substrate pass through chamber, and isolates the substrate from the high cleanliness of the second environment of the substrate pass through chamber.

Abstract: Protective caps are formed over horizontally closely spaced apart metal lines of an integrated circuit structure. Low k silicon oxide dielectric material is then deposited over and between the metal lines and over protective caps on the lines. After the formation of such low k material between the lines and over the caps, standard k dielectric material is deposited over the low k layer as a planarizing layer over low portions of the low k layer between the lines which may be lower than the top of the caps on the lines to prevent further etching or dishing of the low k layer of during planarizing. The structure is then planarized to bring the low k dielectric material down to the tops of the protective caps on the metal lines. A layer of standard k silicon material is then formed over the planarized low k layer and the caps to allow via formation without passing through the low k layer to avoid via poisoning.

Abstract: Via poisoning of vias formed in low k carbon-containing silicon oxide dielectric material is suppressed by forming the via in a layer of such dielectric material with a smooth inwardly sloped sidewall. Such a sloped sidewall via can be etched in a low k dielectric layer by first forming a via resist mask over the upper surface of such a dielectric layer, then heat treating the mask sufficiently to deform the sidewall geometry of the resist mask to form a sloped sidewall on the opening or openings in the heat treated resist mask. The resulting erosion of such a resist mask, during a subsequent etch step to form the via in the low k dielectric material through such a sloped sidewall resist mask, imparts a tapered or sloped sidewall geometry to the via which is then formed in the underlying layer of low k dielectric material.

Abstract: An apparatus comprising a control circuit and a logic circuit. The control circuit may be configured to receive an input signal and an indication signal and present a complement of the input signal. The logic circuit may be configured to receive the complementary input signal and generate an output signal. The output signal may provide full scale voltages between a first supply (e.g., VSS) and a second supply (e.g., VDD2).

Abstract: A process is herein described for analyzing an integrated circuit chip for defects by observing changes in the appearance of a liquid crystal applied to the backside of the integrated circuit. The process includes spreading a thin film of a liquid crystal material on the backside of the integrated circuit. Using an optical microscope, the liquid crystal film is optically inspected as the chip is biased.

Abstract: Provided is a vertically integrated (“chip-over-chip”) semiconductor package and packaging method. The invention provides higher packaging density and performance, including increased functionality, decreased signal propagation delays, improved circuit switching speed, lower thermal resistance and higher thermal dissipation measurements, relative to previous package designs. According to the invention, a semiconductor package may be composed of a flip chip (or chips) overlying one or more other flip chips, all electrically bonded to flip chip bond pads on a cavity-less semiconductor substrate. The upper and lower flips chips may be assembled in a variety of different configurations and may be thermally or electrically connected to each other. In a preferred embodiment, the flip chips, particularly the lower flip chip(s), are thinned so that the overall package height is within conventional ranges for traditional single chip packages.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit generally comprises one or more master amplifiers and a plurality of control amplifiers. The first circuit may be configured to generate a plurality of control signals in response to (i) a first signal related to a desired gain and (ii) a second signal related to a known reference. The second circuit may be configured to generate an output signal in response to (i) an input signal and (ii) the plurality of control signals. The output signal may be amplified with respect to the input signal.

Abstract: A method of reducing power rail transients on integrated circuits. The power rail transients are reduced by controlling clock skew in a manner which minimizes dI/dT current demands. The method provides that the phase of the clock to latches/flip flops is shifted in order to spread out the number of simultaneous switching elements. By controlling the number of simultaneous switching devices, a significant reduction in time rate of current demanded from the power rails can be achieved, thereby reducing the magnitude of VSS/VDD voltage transients due to parasitic inductances and resistances supplying power to the integrated circuit. Theoretically, the entire timing spread of the slack graph for clock skew can be used to control the number of simultaneous switching devices.

Abstract: A method and apparatus for a propagation delay and time calibration. The apparatus includes a ring oscillator having a first set of elements. The apparatus also includes delay units. The ring oscillator is used to generate a clock signal used to measure the delay in signals received at the delay blocks. In the depicted examples, the clock signal generated by the ring oscillator is used to run a counter that counts the delay between a transition in a data signal and a reference signal. Each of the delay units includes a second set of elements matching those of the first set of elements in the ring oscillator. The elements in the set of elements are selected such that they track the period of the ring oscillator signal generated by the ring oscillator. The delay units are used to implement the desired delay.

Abstract: A drum washer has a base, a barrel support structure, and a water delivery system. A hollow drum is turned over and placed on the drum washer by inserting a spray head of the water delivery system through a hole in a top cover of the drum and into the interior of the drum. The barrel support structure holds the drum at a fixed angle while water is sprayed from the spray head onto interior surfaces of the drum. The water rinses the interior surfaces of the drum and drains out the hole in the top cover of the drum.

Abstract: A method of datapath cell placement is disclosed that minimizes signal propagation time through a datapath macro and datapath macro area that includes the steps of receiving as input a datapath description for a datapath block wherein the datapath description describes at least one of a plurality of datapath cells, a plurality of data input pins, a plurality of data output pins, and a plurality of control signal pins; sorting the plurality of data input pins and the plurality of data output pins according to a hierarchy of sorting criteria; determining a plurality of corresponding criticality values for the plurality of datapath cells; sorting the plurality of datapath cells according to the plurality of corresponding criticality values; assigning the plurality of datapath cells to a plurality of corresponding columns; and arranging the plurality of datapath cells within at least one of the plurality of corresponding columns to minimize signal propagation delay through the datapath block.

Abstract: The present invention is a decoder for control gate lines of a twin MONOS flash memory array. Decoder units connected to each control gate line of the memory are controlled to provide select, override and unselect voltages to perform read, program and erase operations. The decoder units are divided into odd and even addressing where separate voltages can be applied control gates of to adjacent memory cells. Override voltages, which prevent operations of a selected cell from affecting adjacent memory cell storage sites, can be applied to the control gates of immediate neighboring cells of the selected sell. Unselected voltages can be applied to beyond the immediate neighboring cells to further prevent disturb conditions in remote cells.

Abstract: A method of testing semiconductor devices on a wafer, including a tasting circuit formed on the wafer for providing an output signal indicative of at least one operational characteristic of the devices. The output signal provided by the testing circuit is compatible for monitoring using an integrated circuit tester. The testing circuit includes an oscillator, an N-bit counter, and an N-bit shift register, all formed on the semiconductor wafer. The tester resets the counter and enables the oscillator, at which time the oscillator produces oscillator pulses at an oscillator frequency. During a predetermined time period, the counter receives and counts the oscillator pulses from the oscillator, and produces a pulse count corresponding to the number of oscillator pulses received. The shift register receives the count from the counter as an N-bit digital data word. The tester shifts the N number of bits of the digital data word out of the shift register, and manipulates the bits to determine a count value.

Abstract: A transportable memory apparatus including cache memory and a backup battery is provided that is capable of being removed from a first computer system and installed within a second computer system. The transportable memory apparatus includes a control bus that provides appropriate signals such that the presence and status of the transportable memory apparatus can be detected in order to permit the computer system that includes the transportable memory apparatus to be appropriately initialized. As such, methods for initializing a computer system that may include a transportable memory apparatus are also provided.

Abstract: An arrangement for polishing a semiconductor wafer is disclosed. The arrangement includes a plurality of preassembled polishing pad assemblies which can be selectively coupled to, and decoupled from, an actuating mechanism for rotating the polishing pad assemblies. An associated method of polishing a semiconductor wafer is also disclosed.

Abstract: A method of forming a via in a circuit, such that parasitic capacitance is reduced. The surface layers of the circuit are identified, to which continuity with the via is desired, and secondary layers of the circuit are also identified. Via lands are formed only on the surface layers and not on the secondary layers. The via lands are formed in first portions of the surface layers, where the via is to pass through the surface layers. Nonconductive cut outs are formed in second portions of the secondary layers where the via is to pass through the secondary layers. The surface layers and the secondary layers of the circuit are laminated together. The first portions of the surface layers are aligned with the second portions of the secondary layers. A through hole is formed through the via lands formed in the surface layers, and also through the cut outs formed in the secondary layers. The via is formed in the through hole.

Abstract: A computer program that improves a netlist of logic nodes and physical placement for an IC. The program (a) identifies critical nodes based on delay information calculated from the physical placement. Then the program (b) selects a set of critical nodes and optimally collapses their critical fan-ins and part of the non-critical fan-ins based on their Boolean relationship, which, includes at least one critical node. After that, the program (c) remaps the collapsed sub-netlist by covering its subject graph with an optimal pattern graph, and dynamically estimates and updates the fanout loads. The program returns to step (b) if the remapped sub-netlist is unacceptable, and returns to step (a) after updating the delay information and coordinates of newly mapped gates if the remapped sub-netlist is acceptable. The program exits at step (a) when no more critical nodes are identified at step (a).

Abstract: The inter-symbol interference problem is reduced by detecting a data sequence indicating when a boost is needed on a ‘short pulse’, usually the first data pulse of the opposite polarity after a string of data pulses of the same value. A data decoder that detects when current compensation is required and an output driver that has the variable drive capability to change the drive current on the short pulse is used to boost the amplitude. The output driver is regulated by a phase locked loop which includes a voltage variable delay digitally controlled voltage variable reference capacitors in the phase locked loop circuit for receiving data from memory that contains the proper capacitor control voltage needed. The time required to charge the capacitor is constant and the delay is slaved to the clock period.