Abstract: An on-chip built-in self test apparatus for a phase locked loop module that resides on an integrated circuit, receives a reference clock signal and provides an output clock signal. The apparatus generally comprises a finite state machine and testing circuitry. The finite state machine may be for (i) receiving the reference clock signal and for (ii) producing testing signals for the phase locked loop module. The testing circuitry may be coupled to the finite state machine for (i) receiving the output clock signal, (ii) determining whether the characteristics of the output clock signal meet a predetermined criteria for open and close loop phase locked loop module operation, and (iii) outputting a test signal that indicates proper phase locked loop module operation if the characteristics of the output clock signal meet the predetermined criteria.

Abstract: The inter-symbol interference problem is reduced by detecting a data sequence indicating when a boost is needed on a ‘short pulse’, usually the first data pulse of the opposite polarity after a string of data pulses of the same value. A data decoder that detects when current compensation is required and an output driver that has the variable drive capability to change the drive current on the short pulse is used to boost the amplitude. The output driver is regulated by a phase locked loop which includes a voltage variable delay digitally controlled voltage variable reference capacitors in the phase locked loop circuit for receiving data from memory that contains the proper capacitor control voltage needed. The time required to charge the capacitor is constant and the delay is slaved to the clock period.

Abstract: An enclosure module for accommodating a plurality of peripheral devices having: a computerized control unit in electrical communication with a user interface, a first and second bus with a bus expansion logic element therebetween that allows for operation of the buses as a single logical bus or as independent buses, termination circuitry for signal-appropriate bus termination, and a first and second plurality of connectors, each for electrical connection with one of the peripheral devices. The user interface to accept a first input (and can include a second, third, fourth, and so on, input) for optional manual configuration of a respective operational feature of the enclosure module, and if the input(s) is not registered, the feature can be automatically configured without the particular information provided by the input. The connectors can each have a multi-connect assembly for connection with a first, second, and third type connector.

Abstract: A clock gating cell and a method of manufacturing the same. In one embodiment, the clock gating cell includes: (1) gate signal and clock signal inputs configured to receive gate enable and clock input signals, respectively, and (2) a gated clock signal output configured to generate a gated clock signal that is a function of states of the gate enable and clock signals, the clock gating cell treated as an atomic entity in a cell library.

Abstract: An inventive semiconductor chip is provided. Generally, shallow trenches containing field oxide are provided on a substrate. At least one semiconductor device is formed between the shallow trenches. An oxide layer is formed over the at least one semiconductor device and the field oxide. An etch stop layer is formed over the oxide layer. An inter layer dielectric layer is formed over the etch stop layer. At least one contact hole is etched through the inter layer dielectric layer, the etch stop layer and at least partially through the oxide layer. The contact hole is filled with a conductive material.

Abstract: A switched gain differential amplifier is provided which includes first and second differential transconductance amplifier stages and a disabled dummy differential transconductance amplifier stage. The first and second differential transconductance amplifier stages have respective differential inputs that are coupled in-phase to one another and respective differential outputs that are coupled in-phase to one another. At least one of the stages is selectively enabled. The disabled dummy differential transconductance amplifier stage has a differential input coupled in-phase to the differential inputs of the first and second differential transconductance amplifier stages and a differential output cross-coupled out-of-phase to the differential outputs of the first and second differential transconductance amplifier stages.

Abstract: The present invention is directed to a heat dissipation structure for an integrated circuit package, comprising a thermally conductive solid layers, one of which has receptacles for holding a thermally conductive flowable material, the heat dissipation structure being placed between the electronic component and the printed circuit board. The present invention is used advantageously with a primary heat sink placed on the top side of the integrated circuit package away from the printed circuit board. The heat dissipation structure preferably hemispherical balls on the package side of a high heat conductive plate to improve heat transfer from the die to the integrated circuit, especially, BGA, substrate to PCB power planes for heat dissipation and leads to improved secondary heat transfer from IC die in BGA packages to the heat spreader power planes in the system PCB. The heat dissipation device allows retro-fit of the heat transfer/transfer mechanism or primary attachment.

Abstract: Sequence number metadata which identifies an input/output (I/O) operation, such as a full stripe write on a redundant array of independent disks (RAID) mass storage system, and revision number metadata which identifies an I/O operation such as a read modify write operation on user data recorded in components of the stripe, are used in an error detection and correction technique, along with parity metadata, to detect and correct silent errors arising from inadvertent data path and drive data corruption. An error arising after a full stripe write is detected by a difference in sequence numbers for all of the components of user data in the stripe. An error arising after a read modify write is detected by a revision number which occurred before the correct revision number.

Abstract: A method of computing timing delays of timing edges of a path of an integrated circuit design. According to the method, all pins within the path are identified, and all timing edges defined by the pins within the path are identified. All pins within the path that are a leading pin of one of the time edge in the path are also identified. For each given pin within the path, a tabulation is made of a number of pins that are upstream from the given pin along a contiguous series of the timing edges in the path. A computational rank is assigned to the given pin based upon the tabulated number for the given pin. The timing edges are ordered for computation based upon the computational rank of the leading pin of each timing edge in the path, to produce an ordered list of timing edges. The timing delays of the timing edges of the path are computed according to the ordered list of timing edges.

Abstract: A binary search tree is structured so that keys or addresses associated with data in the bottom vertices are arranged in a predetermined order, such as ascending key address order. The root vertex and each hierarchy vertex contains the lowest value key from each child vertex and are thus similarly arranged by key value order. Each vertex of each level contains at least k and no more than 2k−1 keys, where k is an integer ≦2 and is constant for all vertices of a given level, but may vary between levels. The result is a structured tree having equal path lengths between the root vertex and each bottom vertex for search purposes. Keys are deleted and inserted to the bottom vertices by restructuring the tree under control of computer instructions.

Abstract: A concentric optical cable and connector capable of full duplex transmission of optically encoded information is disclosed. The concentric optical cable comprises at least a core optical conductor suitable for conducting a light beam encoded with a first set of optically encoded information concentrically disposed about a concentric optical conductor suitable for conducting a light beam encoded with a second set of optically encoded information. The connector includes a first connector portion suitable for connection of the core optical conductor of the optical cable. The first connector portion is substantially concentrically disposed about a second connector portion suitable for connection of the concentric optical conductor of the optical cable thereby providing full duplex transmission of information. In this manner, the optical cable and connectors are capable of full duplex transmission of the first and second sets of optically encoded information.

Abstract: Clock delays are changed in a clock network of an ASIC. Global skew optimization is achieved by restructuring a clock domain to balance clock delays in the domain, and by equalizing clock delays of several domains of a group that have timing paths between them. Clock delays are equalized using buffer chains affecting all leaves of the respective domain, and an additional delay coefficient that equalizes clock delay. The clock insertion delays are changed for each group by restructuring the buffers in the group, based on both the data and clock logics to optimize the paths. Local skew optimization is achieved by restructuring the clock domain using a heuristic algorithm and re-ordering the buffers of the domain. A computer program enables a processor to carry out the processes.

Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

Abstract: A multiport testing procedure capable of detecting faults that occur between static random access memory ports as well as traditional cells faults uncovers all possible faults and covers all cells in the memory, without placing architectural constraints on the memory. While executing a test sequence on one port of the memory array, concurrent memory accesses are performed through other ports in the memory. If a fault exists between the port under test and any other port, then the concurrent operations interfere with the values read and/or written on the port under test, and the test uncovers the fault. Thus, for any one test port, the interport test requires only as many memory operations as the associated single port test, keeping test time to a minimum. One embodiment detects faults between the test port, which is a read/write port, and any other port, including read ports and write ports, comprising six passes through the memory.

Abstract: An intensity filter for deep UV lithography enhances contrast and also therefore increases the resolution of patterned images by passing only intensities that fall within a specific minimum threshold value, resulting in a more exact aerial image replicating the mask image. This device is a different approach to contrast enhancement that is distinguished from previous methods by eliminating the need for an extra layer of contrast enhancement on top of the resist, thereby reducing the number of processing steps in semiconductor fabrication.

Abstract: A deice maximizes the allowable granularity of adjustment of a bus driver line characteristics by compensating for temperature variations by selecting components that have an opposite and approximately equal thermal coefficient. In the first aspect, component parts may be made smaller because their tolerances need not be made so precise. In the second aspect, duplicating the circuitry with matching characteristics allows one circuit to be operational while the other circuit is tested or dormant. Switching between the two circuits is performed seamlessly with no interruption of device operation.

Abstract: A method of synthesizing a clock tree for an integrated circuit design is disclosed that includes the steps of constructing an initial balanced clock tree for an integrated circuit design; calculating a clock arrival time for each clock driven cell in the initial clock tree; performing a timing analysis from the clock arrival time calculated for each clock driven cell; and performing a skew optimization concurrently with the timing analysis to correct timing violations discovered by the timing analysis.

Abstract: Digital interference rejection of a signal is accomplished by first converting the signal to digital. Then a second signal is generated and mixed with the first signal. This combined signal is then filtered. The signal can then be scaled as needed, resulting in a finely tuned, interference free signal.

Abstract: A method of fabricating a substantially completely silicided polysilicon gate electrode in a CMOS process flow. A hard mask material is formed on an integrated circuit substrate, where the integrated circuit substrate includes an unpatterned polysilicon layer that overlies a gate oxide layer, and a well region disposed between isolation structures. Portions of the hard mask material are removed to define gate electrode masks that overlie first portions of the unpatterned polysilicon layer and the gate oxide layer, leaving exposed second portions of the unpatterned polysilicon layer and the gate oxide layer. The integrated circuit substrate is exposed to a dopant that passes through the second portions of the gate oxide layer but does not penetrate the first portions of the gate oxide layer that underlie the gate electrode masks, which defines source drain regions in the well region.

Abstract: A program for improving a netlist of logic nodes and physical placement for an IC. The program (A) identifies critical nodes based on time calculated from a physical placement. The program (B) selects a set of critical nodes and sub-netlists associated with the critical nodes and co-factors critical fan-ins in the sub-netlists. The program remaps the sub-netlists by optimization and dynamically estimates and updates fanout loads. The program returns to step B if the remapped sub-netlist is unacceptable, returns to step A if the remapped sub-netlist is acceptable, and exits at step A when no more critical nodes are identified at step A.