Abstract: Disclosed is an attenuated phase shift reticle design having a compensating transmissive region located where side lobe ringing is anticipated to be most severe. Unlike other transmissive regions on the reticle, no integrated circuit features are defined at the location of the compensating transmissive region. Because the radiation giving rise to side lobe ringing is approximately 180.degree. out of phase with the radiation passing through transmissive regions, radiation passing through the compensating transmissive region will reduce side lobe intensity by destructively interfering with the out of phase radiation. A disclosed reticle defines a plurality of closely packed vias to be formed in a passivating layer. In the case of a positive resist, transmissive regions are provided at locations on the reticle design corresponding to positions of the vias on the passivating layer. A phase shift reticle having such via layout is expected to produce severe side lobe ringing in the regions surrounding the vias.

Abstract: A cell placement for an integrated circuit chip is divided into two "chessboard" patterns or "jiggles". Each pattern resembles a chessboard in that it consists of alternating regions of different types or "colors" such that no region of a given color has an edge common with another region of the same color. The jiggles are offset relative to each other such that the regions of one jiggle partially overlap at least two regions of the other jiggle. Simulated annealing is performed sequentially for each color of each jiggle. During each operation, a plurality of parallel processors operate on the regions simultaneously using a previous copy of the entire chip, with one processor being assigned to one or more regions. At the end of each operation, the copy of the chip is updated. The chessboard patterns eliminate unproductive cell moves resulting from adjacent regions having a common edge. The jiggles enable cells to move to their optimal positions from their initial region to any other region on the chip.

Abstract: A novel configuration for MOS devices employed in a partially generic gate array type chip having large numbers of generally MOS devices. The MOS devices have a non-rectangular configuration and include at least a first and second region of conductivity type differing from the conductivity type of the gate array substrate that are separated by a channel over which an electrode strip such as a gate is formed. The non-rectangular configuration of the MOS devices provides a space savings that permits the presence of a greater number of devices on a single chip as compared to conventional gate array chips. In accordance with another aspect of the invention one or more patternable busses of conductive material, such as polysilicon, interconnect electrode strips of the MOS devices, such as gates strips, that are made of the same conductive material as the busses.

Abstract: A semiconductor device is provided having a circuit for measuring a propagation delay related to metal layers formed on the device. In one embodiment, the circuit includes a first bond pad connected to an input of a first signal path, the first signal path including a first plurality of serially connected logic gates wherein the connection between each logic gate of the first plurality is formed on a first metal layer and a second bond pad connected to an output of a second signal path, the second signal path including a second plurality of serially connected logic gates wherein the connection between each logic gate of the second plurality is formed on a second metal layer, the second signal path being in electrical communication with the first signal path.

Abstract: An integrated circuit having an outer ring of bonding pads which is positioned so as to be adjacent to and concentric with the perimeter of the integrated circuit. The outer ring of bonding pads extends for at least a first portion of the perimeter. An inner ring of bonding pads is positioned interior of, adjacent to, and concentric with the first ring of bonding pads. The inner ring of bonding pads extends for at least a second portion of the perimeter. The first portion is greater than the second portion, or in other words, the outer ring of bonding pads extends further around the integrated circuit than the inner ring of bonding pads. In addition, the outer ring of bonding pads has a greater number of bonding pads that the inner ring of bonding pads. Traces are electrically connected to the bonding pads of the inner and outer rings, such that each pad is electrically connected to a unique trace, meaning that each pad has a trace which is associated with just that pad and with no other pad.

Abstract: A wireless communication unit for a wireless communication system transmits and receives video and audio signals over an RF bandwidth. The RF bandwidth is allocated among the audio and video signals to allow the audio and video signals to fit within the RF bandwidth. The allocation is performed by varying the rates of compression of the audio and video signals. The communication unit is applicable to subscriber units and base stations. Subscriber units such as cellular telephones can display the video images by using fast digital-to-analog converters and a dither technique. During a communication link, the subscriber unit receives a transmission header from another party on the communication link. The transmission header may include a request by the other party to change the allocation of the audio and video signals. If such a request is received, the subscriber unit automatically changes the allocation in response to the request.

Abstract: A large number of possible placements of cells on an integrated circuit chip are generated and evaluated to determine the placement with the highest fitness. Cells for transposition or "swapping" within each placement using genetic algorithms are selected using greedy algorithms based on the fitness of each cell. The cell fitnesses are evaluated in terms of interconnect congestion, total net wire length or other criteria. Cells are selected for genetic crossover by sorting the cells in order of fitness and multiplying the cell fitnesses by weighting factors that increase non-linearly with rank. The cells are selected using linear random number generation such that cells with higher fitnesses have a higher probability of selection. Cells having lowest fitness are selected for mutation, and transposed to random locations, to adjacent locations, with cells having second worst fitness, to the center of mass of the respective interconnect nets, or with two or more cells in a cyclical manner.

Abstract: A semiconductor device package containing a semiconductor die uses a platform mounted on an active face of the die. The platform electrically connects to at least one bond pad on the die. A package lid electrically connects to the platform on the die and a package case connection. The package case connection is also electrically connected to at least one external connector on the package. The platform and package lid thereby connect the at least one bond pad on the die to the at least one external connector on the package. Using the platform and lid for electrical connections from the semiconductor die bond pads to the external package connector reduce the number of bond fingers required to surround the perimeter of the die. The package lid and platform may, for example, be used for ground or power connections to the die bond pads.

Abstract: A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set including 16-bit and 32-bit instructions. The 32-bit instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e.g. 32 bit) instruction. The compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields. Certain select instructions are assigned two opcode encodings, one for each of two mappings of the corresponding register fields. The compressed register field is directly copied into a portion of the decompressed register field while the remaining portion of the decompressed register field is created using a small number of logic gates.

Abstract: An integrated circuit package having a die supported on a ball grid array substrate and wire bonds electrically connecting the die to the substrate. Supported on the substrate is a lock ring having a threaded opening encircling the die. Encapsulant covers the die and the wire bonds and adheres the lock ring to the substrate. A heat sink having a threaded portion can be threaded into the lock ring into an operative cooling position relative to the die and subsequently to an unthreaded removed position. When in the latter position, a repair station can be positioned over the package and the solder balls are accessible for hot gas melting thereof for removal (or replacement) of the package from the underlying motherboard.

Abstract: A process and apparatus are described for inhibiting, but not completely eliminating, the deposition of titanium nitride by MOCVD on the end edge of a semiconductor substrate which comprises directing toward such substrate end edge a flow of one or more deposition-inhibiting gases in a direction which substantially opposes the flow of process gases toward the end edges of the substrate. This flow of deposition-inhibiting gases toward the end edges of the substrate reduces the deposition of the titanium nitride at the end edge of the semiconductor substrate either by directing some of the flow of process gases away from such end edge of the substrate, or by locally diluting such process gases in the region of the deposition chamber adjacent the end edge of the substrate, or by some combination of the foregoing.

Abstract: A surface mounted integrated circuit die package includes a group of peripheral leads extending laterally outwardly from the perimeter of the package and also includes an array of solder balls on the bottom of the package. The arrangement provides for a greater number of input/output connections to a die package by utilizing both peripheral leads and a ball grid array without requiring increases in package size or a reduction in the width of electrically conductive interconnections.

Abstract: A method and apparatus for improving the phase granularity when changing the phase of a digital signal. The present invention doubles the phase shift granularity of a phase shifting system by either adding or not adding one-half unit of phase delay to the digital signal being phase shifted. When increasing phase delay is being added to the digital signal, no additional phase delay is added to the digital signal. When decreasing phase delay is being adding to the digital signal, one-half unit of phase delay is added to the digital signal. Thus, whenever a change is made between increasing or decreasing phase delay, a one-half unit phase delay is introduced which effectively doubles the phase delay granularity of the phase delay system at the point of phase delay reversal.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: A test method and means for in integrated circuit (10) having asynchronous communication capabilities including a transmitter (12) and a receiver (14). A pattern generator (24) is provided for generating patterns directly from within the integrated circuit (10). In the best presently known embodiment, a serializer (16) provides a serial output (20) and a deserializer (18) processes a serial input (22) into a parallel signal and provides the parallel signal to a receiver (14). The pattern generator (24) is preprogrammed to provide a parallel data pattern which can optionally and intermittently be provided to the transmitter (12) in a test mode (44). In the test mode (44), signal is routed from the serializer (16) directly to the deserializer (18) via an external loop back path (34) or an internal alternative loop back path (34a).

Abstract: A first metal layer is formed on a substrate of an integrated circuit and electrically interconnects a microelectronic device and an Input/Output (I/O) pad. A second metal layer is insulated from the first metal layer by a dielectric layer, and is connected directly only to the pad. A plurality of vias are formed through the dielectric layer, and electrically interconnect the first and second metal layers such that current can flow between the device and the pad through both metal layers and the vias. A higher scale of circuit integration is made possible by reducing the widths of the metal layers without reducing their combined current carrying capacity. An Electrostatic Discharge (ESD) protection device is connected to one or both of the first and second metal layers such that current can flow from the pad to the protection device during an ESD event through both metal layers and the vias.

Abstract: A loop back test system and method for providing local fault detection within the core or macrocell of an integrated I/O interface device on an integrated circuit is disclosed. The system and method of this invention is suitable for use in any I/O interface having both a transmitter and a receiver section. The loop back of input test data from the transmitters output directly to the receiver's input permits fault detection within the core of an integrated I/O interface. By illustration, in a serializer/deserializer I/O, the loop back of serialized, alignment pattern encoded parallel data from the output stage of the I/O transmitter to the receiver's input stage permits identifying faults occurring within the integrated I/O transceiver macrocell. The loop back test system and method of this invention permits fault isolation of within the boundaries of the I/O core and independent of external logic or testers.

Abstract: A driver circuit that is powered by a power supply voltage has an output terminal, and includes a pull-up transistor for pulling the output terminal up toward the power supply voltage. A voltage divider that is connected across the power supply voltage has a tap connected in circuit to an input of the pull-up transistor and includes variable resistance elements whose resistance varies together with a threshold voltage of the pull-up transistor for limiting a voltage at the output terminal to within a predetermined range that is lower than the power supply voltage.

Abstract: A method for cleaning solder bumps on a substrate that may be employed in a flip-chip design, for example, is described. The method of cleaning includes placing the substrate having the solder bumps into a plasma reactor, introducing a source gas including nitrogen trifluoride gas into the plasma reactor, striking a plasma from the source gas in the plasma reactor, and forming a fluoride compound on the surface of the solder bump.

Abstract: A phase locked loop includes a voltage controlled oscillator (VCO) for generating output VCO pulses. A frequency divider divides the VCO pulses by a variable number to produce frequency divided pulses whose phase is compared with that of input reference pulses by a phase detector. An update pulse is produced by the phase comparator having a pulsewidth corresponding to the detected phase difference. A pulse generator generates a train of update pulses having a combined pulsewidth equal to the pulsewidth of the update pulse, with the update pulses being substantially equally distributed within each period of the reference pulses to produce low output ripple. The update pulses are integrated by a loop filter to produce a D.C. control voltage that controls the VCO to vary the frequency of the VCO pulses such that the phase difference is adjusted toward zero. The frequency divider comprises a binary counter and a controller that enable the frequency divider to divide by a number N that is not a power of 2.