Abstract: A process for heat treating a silicon wafer to dissolve B-type agglomerated interstitial defects present therein. The process includes heating the silicon wafer at a temperature for a time sufficient to dissolve B-defects, the wafer being heated to said temperature at a rate sufficient to prevent B-defects from becoming stabilized such that these defects are rendered incapable of being dissolved.
Type:
Grant
Filed:
September 14, 2000
Date of Patent:
October 21, 2003
Assignee:
MEMC Electronic Materials, Inc.
Inventors:
Luciano Mule'Stagno, Jeffrey L. Libbert, Joseph C. Holzer
Abstract: The present invention is directed to a single crystal Czochralski-type silicon wafer, and a process for the preparation thereof, which has a non-uniform distribution of crystal lattice vacancies therein, the peak concentration being present in the wafer bulk between an imaginary central plane and a surface of the wafer, such that, upon being subjected to the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, the wafer forms oxygen precipitates in the wafer bulk and a thin or shallow precipitate-free zone near the wafer surface.
Type:
Application
Filed:
October 22, 2002
Publication date:
October 16, 2003
Applicant:
MEMC Electronic Materials, Inc.
Inventors:
Jeffrey L. Libbert, Martin Jeffrey Binns, Robert J. Falster
Abstract: The present invention relates to an epitaxial wafer comprising single crystal silicon substrate and an epitaxial layer deposited thereon. The substrate comprises an axially symmetric region which is free of agglomerated intrinsic point defects and wherein silicon self-interstitials are the predominant intrinsic point defect in the axially symmetric region. The present invention further relates to a process for producing such an epitaxial wafer.
Type:
Grant
Filed:
April 30, 2002
Date of Patent:
October 14, 2003
Assignee:
MEMC Electronic Materials, Inc.
Inventors:
Robert A. Falster, Joseph C. Holzer, Steve A. Markgraf, Paolo Mutti, Seamus A. McQuaid, Bayard K. Johnson
Abstract: A method for estimating the likely waviness of a wafer after polishing based upon an accurate measurement of the waviness of the wafer in an as-cut condition, before polishing. The method measures the thickness profile of an upper and lower wafer surface to construct a median profile of the wafer in the direction of wiresaw cutting. The median surface is then passed through an appropriate Gaussian filter, such that the warp of the resulting profile estimates whether the wafer will exhibit unacceptable waviness in a post-polished stage.
Type:
Application
Filed:
March 7, 2002
Publication date:
September 11, 2003
Applicant:
MEMC Electronic Materials, Inc.
Inventors:
Milind S. Bhagavat, Yun-Biao Xin, Gary L. Anderson, Brent F. Teasley
Abstract: An apparatus for slicing semiconductor wafers from a single-crystal ingot includes a web of wire for slicing the ingot into wafers and a frame having a head for supporting the ingot during slicing. The apparatus further includes a controller and a temperature sensor disposed in the head and operable to send a signal to the controller indicating head temperature. The controller is operable to control temperature of a fluid directed to the head in response to the signal thereby to control the head temperature. Methods of slicing wafers are also disclosed.
Type:
Application
Filed:
February 28, 2003
Publication date:
September 11, 2003
Applicant:
MEMC Electronic Materials, Inc.
Inventors:
Milind S. Bhagavat, Dale A. Witte, Steven L. Kimbel, David A. Sager, John W. Peyton
Abstract: A method for estimating the likely waviness of a wafer after polishing based upon an accurate measurement of the waviness of the wafer in an as-cut condition, before polishing. The method measures the thickness profile of an upper and lower wafer surface to construct a median profile of the wafer in the direction of wiresaw cutting. The median surface is then passed through an appropriate Gaussian filter, such that the warp of the resulting profile estimates whether the wafer will exhibit unacceptable waviness in a post-polished stage.
Type:
Grant
Filed:
March 7, 2002
Date of Patent:
September 2, 2003
Assignee:
MEMC Electronic Materials, Inc.
Inventors:
Milind S. Bhagavat, Yun-Biao Xin, Gary L. Anderson, Brent F. Teasley
Abstract: This invention is directed to a novel process for the preparation of a silicon wafer comprising a surface having an epitaxial layer deposited thereon. In one embodiment, an epitaxial layer is deposited onto a surface of a silicon wafer. The wafer is also heated to a temperature of at least about 1175° C. This heat treatment begins either during or after the epitaxial deposition. Following the heat treatment, the heated wafer is cooled for a period of time at a rate of at least about 10° C./sec while (a) the temperature of the wafer is greater than about 1000° C., and (b) the wafer is not in contact with a susceptor. In this process, the epitaxial deposition, heating, and cooling are conducted in the same reactor chamber.
Type:
Application
Filed:
March 19, 2003
Publication date:
August 28, 2003
Applicant:
MEMC Electronic Materials, Inc.
Inventors:
Charles Chiun-Chieh Yang, Darrell D. Watkins
Abstract: A granular semiconductor material transport system capable of continuous, non-contaminating transfer of granular semiconductor material from a large source vessel to a smaller and more manageable target vessel. Movement of the granular material is induced by flowing transfer fluid. The system includes a source vessel, a feed tube, a process vessel, a target vessel and a vacuum source, or mover. The source vessel contains a bulk supply of granular material to be transported. A feed tube received within the source vessel transfers the granular material entrained in a transfer fluid from the source vessel to the process vessel. The process vessel separates the granular material from any dust particles and deposits the granular material in the more manageable target vessel. The vacuum source sealably connects to the process vessel to evacuate the process vessel to set the granular polysilicon in motion within the system.
Type:
Grant
Filed:
October 23, 2001
Date of Patent:
August 26, 2003
Assignee:
MEMC Electronic Materials, Inc.
Inventors:
Dick S. Williams, Howard VanBooven, Jimmy D. Kurz, Timothy J. Kulage
Abstract: The present invention relates to a single crystal silicon, in wafer and ingot form, which contains an axially symmetric region which is free of agglomerated intrinsic point defects. The region extends from a circumferential edge of the wafer or constant diameter region of an ingot, axially inwardly toward a central axis such that the entire wafer, a constant diameter portion of the ingot, or an annular-shaped portion of wafer or ingot is free of agglomerated intrinsic point defects. The present invention further relates to these axially symmetric regions wherein silicon self-interstitials are the predominant intrinsic point detect.
Abstract: A process for detecting mechanical and mechanochemical defects in the surface or edge of a silicon wafer resulting from a wafer manufacturing process. The present process comprises treating a surface of the silicon wafer with an aqueous etch solution comprising hydrofluoric acid and an oxidizing agent, followed by optical inspection of the treated wafer surface prior to subjecting that surface to conventional mechanical or mechanochemical polishing. The present process affords the means by which to more efficient identify wafers having such defects, thus reducing wafer manufacturing time and cost.
Type:
Grant
Filed:
April 5, 2000
Date of Patent:
July 29, 2003
Assignee:
MEMC Electronic Materials, Inc.
Inventors:
Anca Stefanescu, Zhijian Pei, Henry F. Erk, Tom Doane
Abstract: An apparatus and method for forming an epitaxial layer on and a denuded zone in a semiconductor wafer. A single chamber is used to form both the epitaxial layer and the denuded zone. The denuded zone is formed by heating the wafer in the chamber and then rapidly cooling the wafer while it is supported on an annular support whereby only a peripheral edge portion of the wafer is in contact with the support.
Abstract: A silicon wafer having a controlled oxygen precipitation behavior such that a denuded zone extending inward from the front surface and oxygen precipitates in the wafer bulk sufficient for intrinsic gettering purposes are ultimately formed. Specifically, prior to formation of the oxygen precipitates, the wafer bulk comprises dopant stabilized oxygen precipitate nucleation centers. The dopant is selected from a group consisting of nitrogen and carbon and the concentration of the dopant is sufficient to allow the oxygen precipitate nucleation centers to withstand thermal processing such as an epitaxial deposition process while maintaining the ability to dissolve any grown-in nucleation centers.
Type:
Application
Filed:
December 23, 2002
Publication date:
July 24, 2003
Applicant:
MEMC Electronic Materials, Inc.
Inventors:
Luciano Mule'Stagno, Jeffrey L. Libbert, Richard J. Phillips, Milind Kulkarni, Mohsen Banan, Stephen J. Brunkhorst
Abstract: A single crystal silicon wafer with a back surface free of an oxide seal and substantially free of a chemical vapor deposition process induced halo and an epitaxial silicon layer on the front surface, the epitaxial layer is characterized by an axially symmetric region extending radially outwardly from the central axis of the wafer toward the circumferential edge of the wafer having a substantially uniform resistivity, the radius of the axially symmetric region being at least about 80% of the length of the radius of the wafer.
Type:
Grant
Filed:
December 29, 2000
Date of Patent:
July 22, 2003
Assignee:
MEMC Electronic Materials, Inc.
Inventors:
Michael J. Ries, Charles Chiun-Chieh Yang, Robert W. Standley
Abstract: A method and system for determining polycrystalline silicon chunk size for use with a Czochralski silicon growing process. Polycrystalline silicon chunks are arranged on a measuring background. A camera captures an image of the chunks. An image processor processes the image and determines the dimensions of the chunks based on the captured image. A size parameter associated with the chunks is determined.
Type:
Grant
Filed:
October 15, 1999
Date of Patent:
July 8, 2003
Assignee:
MEMC Electronic Materials, Inc.
Inventors:
John D. Holder, Steven Joslin, Hariprasad Sreedharamurthy, John Lhamon
Abstract: A process for heat-treating a single crystal silicon wafer to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step. The wafer has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the wafer is subjected to a heat-treatment to form crystal lattice vacancies in the wafer. During the heat-treatment, the front and back surfaces of the wafer are each exposed to either a nitriding or non-nitriding gas. The wafer is then cooled from the temperature of said heat treatment at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a wafer having a vacancy concentration profile determined in part by the gas that each surface is exposed to and in part by the cooling rate.
Type:
Grant
Filed:
November 2, 2000
Date of Patent:
July 1, 2003
Assignee:
MEMC Electronic Materials, Inc.
Inventors:
Robert Falster, Marco Cornara, Daniela Gambaro, Massimiliano Olmo
Abstract: A process for growing a single crystal silicon ingot having an axially symmetric region substantially free of agglomerated intrinsic point defects. The ingot is grown generally in accordance with the Czochralski method; however, the manner by which the ingot is cooled from the temperature of solidification to a temperature which is in excess of about 900° C. is controlled to allow for the diffusion of intrinsic point defects, such that agglomerated defects do not form in this axially symmetric region. Accordingly, the ratio v/G0 is allowed to vary axially within this region, due to changes in v or G0, between a minimum and maximum value by at least 5%.
Type:
Application
Filed:
September 30, 2002
Publication date:
June 26, 2003
Applicant:
MEMC Electronic Materials, Inc.
Inventors:
Robert J. Falster, Vladimir Voronkov, Paolo Mutti
Abstract: A heat shield assembly for use in a crystal puller has an outer reflector interposed between the ingot and the crucible as the ingot is pulled from the molten source material. A cooling shield is interposed between the ingot and the outer reflector whereby the cooling shield is exposed to heat radiated from the ingot for increasing the rate at which the ingot is cooled, thereby increasing the axial temperature gradient of the ingot. In a further embodiment, an inner shield panel is disposed generally intermediate the cooling shield and the ingot in radially spaced relationship with the cooling shield and is constructed of a material substantially transparent to radiant heat from the ingot.
Type:
Grant
Filed:
March 23, 2001
Date of Patent:
June 17, 2003
Assignee:
MEMC Electronic Materials, Inc.
Inventors:
Lee W. Ferry, Richard G. Schrenker, Mohsen Banan
Abstract: A process for heat-treating a single crystal silicon wafer to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step. The wafer has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the wafer is subjected to a heat-treatment to form crystal lattice vacancies in the wafer. During the heat-treatment, the front and back surfaces of the wafer are each exposed to either a nitriding gas or a non-nitriding gas. The front surface of the heat-treated wafer is then oxidized by heating in the presence of an oxygen-containing atmosphere in order to further effect the vacancy concentration profile within the wafer.
Abstract: A process for preparing a silicon melt in a crucible for use in growing a single crystal silicon ingot by the Czochralski method. The crucible is first loaded with chunk polycrystalline silicon and heated to partially melt the load. Granular polycrystalline silicon is then fed onto the exposed unmelted chunk polycrystalline silicon to complete the charge of silicon in the crucible. The granular polycrystalline silicon is intermittently delivered using a plurality of alternating on-periods and off-periods. During each on-period, granular polycrystalline silicon is flowed through a feed device that directs the granular polycrystalline silicon onto the unmelted chunk polycrystalline silicon. During each off-period, the flow of the granular polycrystalline silicon is interrupted. The loaded chunk polycrystalline silicon and the fed granular polycrystalline silicon are melted to form the silicon melt.
Abstract: A process of removing metallic impurities from a polished boron-doped silicon wafer comprising forming an oxide layer on the polished wafer that is thicker than a typical native oxide layer so that the oxide layer has a greater gettering capacity than a native oxide layer gettering capacity and then annealing the wafer at a temperature of at least about 75° C. for at least about 30 seconds to decrease the concentration of the metallic impurity in the interior of the silicon wafer and increase the concentration of the metallic impurity on the polished surface of the silicon wafer and in the oxide layer. Preferably, the annealed silicon wafer is cleaned to remove the oxide layer and to remove the metallic impurity from the polished surface of the silicon wafer. By repeatedly creating an oxide layer and annealing the wafer, the wafer can be made substantially free of metallic impurities.
Type:
Application
Filed:
November 13, 2002
Publication date:
June 5, 2003
Applicant:
MEMC Electronic Materials, Inc.
Inventors:
Andrei D. Stefanescu, Leonard O. Rosik, Tina L. Gardner