Abstract: A first host data item and a second host data item are received. The first host data item is stored in a first page of a first logical unit of a memory device, where the first page is one of a plurality of pages associated with redundancy metadata. A second page a second page of a second logical unit of the memory device is identified, where the second page is one of the plurality of pages associated with the redundancy metadata, and the first page and the second page are associated with different wordlines of the memory device. The second host data item is stored in the second page of the second logical unit of the memory device. The first page and the second page can be associated with a fault tolerant stripe that includes the redundancy metadata.

Abstract: Systems, devices, and methods related to generating instructive actions based on categorization of input data are described. In an example, a method can include receiving, from an edge device and at a processing resource of a device, a plurality of input data associated with a plurality of sources communicatively coupled to the edge device and categorizing each piece of the plurality of input data as private or public based on an associated one of the plurality of sources. The categorizing can include writing each piece of data with metadata that indicates that it is private or public and/or selecting a first data path indicated as private or a second data path indicated as public. The method can include writing each piece of the plurality of input data categorized as private to a dedicated buffer or a dedicated address space of a memory resource.

Abstract: Methods, systems, and devices for techniques for enhanced read performance on blocks of memory cells are described. The method may involve selecting a first block of memory cells from a set of blocks of memory cells of a memory system based on a condition of the first block of memory cells being met and setting one or more programming parameters corresponding to the first block of memory cells such that the one or more programming parameters are within a threshold value of one or more programming parameters corresponding to a second block associated with a storage density different from a storage density of the first block of memory cells. Further, the method may involve performing an operation on the block of memory cells according to the one or more programming parameters.

Abstract: A system receives, via a graphical user interface (GUI), a user selection of one or more parameters indicative of a request to segment the memory device into partitions for use by a host system. Responsive to receiving, via the GUI, the user selection of the one or more parameters indicative of the request to segment the memory device into the partitions, the system configures a first partition of the partitions with one or more configuration settings based on the one or more parameters. To configure the first partition, the system determines a memory type from multiple memory types based on the one or more parameters, and configures the first partition of the partitions to operate as the determined memory type.

Abstract: Disclosed in some examples, are methods, systems, and machine-readable mediums in which application state is saved using in-memory versioning in a shared memory pool of disaggregated memory. By utilizing a disaggregated memory pool, the processing resources may be on separate devices than the memory those resources are using. As a result of this architecture, a failure of hardware of processing resources or an application does not necessarily also cause the hardware resources of the memory devices to fail. This allows a standby application executing on standby processing resources to quickly resume execution when a primary application fails by utilizing the memory pool assigned to the primary application in the memory pool.

Abstract: Methods, systems, and devices for word line structures for three-dimensional memory arrays are described. A memory device may include word line structures that support accessing memory cells arranged in a three-dimensional level architecture. The word line structures may be arranged above a substrate and be separated from each other by respective dielectric layers. Each word line structure may include word line members and a word line plate that is connected to each word line member. Each word line plate may include a contact that may be coupled with a word line decoder operable to bias the word line plate. To couple the word line plate to the word line decoder, the memory device may include first vias that extend through holes in the word line plates and are coupled with second vias that extend from a respective contact through openings in the word line plates above the contact.

Abstract: Methods, systems, and devices for memory system standby mode control are described. A system may be configured to support a memory system transmitting an indication of a duration to a host system in response to receiving a standby indication from the host system. For example, a memory system may determine a set of background operations to be performed at the memory system and, in response to a standby indication, may determine a duration associated with performing at least a subset of the set of background operations. In response to receiving the indication of the duration, the host system may delay an isolation of the memory system from one or more voltage sources, which may include the host system signaling an approval or a different duration to the memory system, during which the memory system may proceed with at least some of the determined set of background operations.

Abstract: Devices and techniques are disclosed herein for providing L2P information to a host device from a storage system, the L2P information comprising a response information unit having a limited size with separate categories of information including changed L2P region and associated subregion information, to-be-loaded L2P region and associated subregion information, and invalid L2P region and associated subregion information, wherein the information in the separate categories is based on the determined changes in the different L2P regions and the subregion information in each of the separate categories identifies specific locations of changed subregions with respect to one or more corresponding regions identified in the region information of a respective category of the response information unit.

Abstract: Methods, systems, and devices for temperature-dependent refresh operations are described. A memory system may adjust refresh operations based on a temperature of the memory system to reduce a refresh current and improve reliability of the refresh operations. For example, the memory system may include a temperature sensor configured to provide temperature information associated with a memory device. Based on the temperature information, the memory system may, in response to a refresh command, activate a set of access lines (e.g., word lines) to refresh memory cells coupled with the access lines, where a count of the set of access lines (e.g., how many access lines are included in the set) may be based on the temperature information. In some examples, the count of the set may be determined based on comparing the temperature information to one or more temperature thresholds.

Abstract: Methods, systems, and devices for idle mode temperature control for memory systems are described. A memory system may implement the use of one or more dummy access commands to reduce the effects of errors introduced by temperature changes while the memory system is in an idle mode. For example, performing one or more access commands, such as one or more read commands, may increase a temperature of a memory device and support a desired operating temperature for the memory device while the memory system is in the idle mode. The memory system may measure the temperature of the memory device during the idle mode. If the memory system determines that the temperature of the memory device has fallen below a threshold temperature, the memory system may issue a quantity of dummy access commands to the memory device, and the corresponding dummy access operations may result in a temperature increase at the memory device.

Abstract: One or more trim values associated with a set of blocks of a memory device are set according to a representative number of program erase cycles (PECs) for the set of blocks. Each block in the set of blocks was programmed within at least one of a specified time window or a specified temperature range. Responsive to executing a program operation on a block of the set of blocks according to the one or more trim values, an indicator is set to reflect the one or more trim values used during the execution of the program operation. Responsive to receiving a request to perform a read operation directed to the block of the set of blocks, a read offset value corresponding to the indicator is determined. The read operation is performed using the read offset value.

Abstract: Methods, systems, and devices for plasma-doped trenches for memory are described. A method for forming a memory device with plasma-doped trenches may include forming a stack of materials having alternating layers of polysilicon and oxide materials. A trench may be etched in the stack and doped using a plasma doping process. In some examples, the trench may be doped by applying Boron fluoride, diborane, methane, or Boron and Carbon Hydride gases diluted with Hydrogen (H2) or Helium to the sidewalls and bottom surface of the trench, which may dope portions of the polysilicon material with Boron, Carbon, Fluorine, Helium, or Hydrogen.

Abstract: Methods, systems, and devices for low-power boot-up for memory systems are described. A memory system may be configured to receive, over a first conductive path of a second communication interface, a first indication to boot-up a memory system and a first communication interface associated with the memory system, wherein the first communication interface includes a plurality of conductive paths; receive, over a second conductive path of the second communication interface, a second indication whether to perform a boot-up operation of the memory system using a low-power mode or a high-power mode based at least in part on receiving the first indication; and boot the memory system according to the low-power mode or the high-power mode based at least in part on receiving the second indication.

Abstract: Methods, systems, and devices for triple activate command row address latching are described. For instance, a memory device may receive a first activate command that indicates a first set of bits of a row address, a second activate command that indicates a second set of bits of the row address, and a third activate command that indicates a third set of bits of the row address. The memory device may activate a page of memory based on receiving the first activate command, the second activate command, and the third activate command, where the page of memory is addressed according to the first set of bits, the second set of bits, and the third set of bits.

Abstract: Methods, systems, and devices for adaptive block mapping are described. In some examples, a first superblock and a second superblock may be established across one or more dice of a memory device. The superblocks may each include one or more blocks from a plurality of planes of a memory die. In some examples, the second superblock may include at least one bad block (e.g., defective block) in addition to one or more good blocks (e.g., non-defective blocks). The memory device may receive a command for writing data in a first mode and may write a first subset of the data to the first superblock in the first mode, a second subset of the data to the second superblock in the first mode, and one or more blocks associated with the second superblock in a second mode. Additionally or alternatively, the memory device may receive a second command for writing data in the second mode and may write the data to the first superblock in the first mode.

Abstract: A threshold criterion of a plurality of threshold criteria is identified based on a current program-erase cycle (PEC) count of a first block of a memory device, wherein the first block is configured as quad-level cell (QLC) memory. A raw bit error rate (RBER) associated with data of a second block of the memory device is determined, wherein the second block is configured as single-level cell (SLC) memory. It is determined that the RBER associated with the data of the second block satisfies the threshold criterion. In response to determining that the RBER satisfies the threshold criterion, the data of the second block is written to the first block.

Abstract: Methods, systems, and devices for signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In various examples, accessing the memory device may include accessing information from the signal development cache, or the memory array, or both, based on various mappings or operations of the memory device.

Abstract: Methods, systems, and devices for verification of a volatile memory, such as a dynamic random-access memory (DRAM), using a unique identifier (ID) are described. A memory device may store a unique ID for a DRAM component of the memory device in non-volatile memory (e.g., in the DRAM, external to the DRAM). A host device coupled with the memory device may store, to non-volatile memory at the host device, information for verifying the identity of the DRAM component, for example, based on the unique ID. The memory device and host device may perform a procedure for verification of the identity of the DRAM component using the unique ID of the DRAM and the verification information stored at the host device. If the host device detects that the DRAM has been replaced or modified based on the verification procedure, the host device may disable one or more features of the memory device.

Abstract: In a memory controller system, a system and method to identify memory errors which may require soft package repair or hard package repair to rows of DRAM memory. When data is written to a row of DRAM, the data is immediately and automatically read back and scanned for bit errors. If bit errors are identified, the data is corrected and written back to the same memory location. The memory location is re-read. If bit errors are again identified, the memory location is marked for soft or hard repair. If, upon rereading the memory location, additional bit errors are identified, a historical record of memory errors is reviewed to determine if bit errors have occurred previously at the same memory location. If yes, the memory location is again marked for a soft post package repair or a hard post package repair.

Abstract: A global lock is used to access a first set of data structures. An active transaction having a transaction start identifier is identified as a globally oldest active transaction associated with the first set of data structures. A first marker value of a first data structure of a second set of data structures is compared to the transaction start identifier to determine satisfaction of a first condition. In response to satisfying the first condition, the first data structure is accessed to identify a first set of data locks associated with one or more transactions each having a transaction completion identifier that satisfies a second condition when compared to the transaction start identifier. In response to satisfying the second condition, the first set of data locks is released.