Patents Assigned to Micronics
  • Array of memory cells, methods used in forming an array of memory cells, methods used in forming an array of vertical transistors, and methods used in forming an array of capacitors
    Patent number: 12342533
    Abstract: A method used in forming an array of memory cells comprises forming a vertical stack comprising transistor material directly above and directly against a first capacitor electrode material. A mask is used to subtractively etch both the transistor material and thereafter the first capacitor electrode material to form a plurality of pillars that individually comprise the transistor material and the first capacitor electrode material. Capacitors are formed that individually comprise the first capacitor electrode material of individual of the pillars. Vertical transistors are formed above the capacitors that individually comprise the transistor material of the individual pillars. Other aspects and embodiments are disclosed, including structure independent of method.
    Type: Grant
    Filed: December 8, 2023
    Date of Patent: June 24, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Antonino Rigano
  • Microelectronic devices, and methods of forming microelectronic devices
    Patent number: 12341134
    Abstract: A microelectronic device comprises a first control logic region comprising first control logic devices and a memory array region vertically overlying the first control logic region. The memory array region comprises capacitors, access devices laterally neighboring and in electrical communication with the capacitors, conductive lines operatively associated with the access devices and extending in a lateral direction, and first conductive pillars operatively associated with the access devices and vertically extending through the memory array region. The microelectronic device further comprises a second control logic region comprising second control logic devices vertically overlying the memory array region. Related microelectronic devices, memory devices, electronic systems, and methods are also described.
    Type: Grant
    Filed: September 29, 2023
    Date of Patent: June 24, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Yuan He
  • Circuitry borrowing for memory arrays
    Patent number: 12340832
    Abstract: Methods, systems, and devices for circuitry borrowing in memory arrays are described. In one example, a host device may transmit an access command associated with data for a first memory section to a memory device. The first memory section may be located between a second memory section and a third memory section. A first set of circuitry shared by the first memory section and the second memory section may be operated using drivers associated with the first memory section and drivers associated with the second memory section. A second set of circuitry shared by the first memory section and the third memory section may be operated using drivers associated with the first memory section and drivers associated with the third memory section. An access operation may be performed based on operating the first set of circuitry and the second set of circuitry.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: June 24, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Martinelli, Francesco Mastroianni, Kiyoshi Nakai
  • Memories for performing successive programming operations
    Patent number: 12340851
    Abstract: Memories might include a controller configured to cause the memory to prepare a first plurality of memory cells of a block of memory cells for programming from an initialization state of the block of memory cells, program the first data to the first plurality of memory cells, and, in response to receiving a write command associated with a second address corresponding to the block of memory cells and with second data before successfully verifying programming of the first data to the first plurality of memory cells, prepare a second plurality of memory cells of the block of memory cells corresponding to the second address for programming without returning the block of memory cells to the initialization state after programming the first data to the first plurality of memory cells.
    Type: Grant
    Filed: February 16, 2023
    Date of Patent: June 24, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Umberto Siciliani, Violante Moschiano, Walter Di Francesco, Dheeraj Srinivasan
  • APPARATUSES AND METHODS FOR CONDUCTIVE COUPLING OF BIT LINES USING BIT LINE SWITCHES
    Publication number: 20250201299
    Abstract: Apparatus and methods for providing a conductive path between bit lines using bit line switches are disclosed. An example apparatus includes a memory mat comprising a first plurality of bit lines and a second plurality of bit lines. A plurality of bit line switches can be activated to provide a conductive path between respective ones of the first plurality of bit lines and a second plurality of bit lines. For example, the bit line switches can be activated during a threshold voltage compensation phase or operation and deactivated during a memory cell activation phase or operation.
    Type: Application
    Filed: July 18, 2024
    Publication date: June 19, 2025
    Applicant: Micron Technology, Inc.
    Inventors: Jiyun Li, Tae H. Kim
  • METHOD AND SYSTEM FOR ON-ASIC ERROR CONTROL ENCODING
    Publication number: 20250199908
    Abstract: Provided are methods and systems for on-ASIC error control coding for verifying the integrity of data from a memory. There is provided a method for encoding data into a beat that can be executed by a digital system to receive the data and construct the beat. The method includes assembling a plurality of words consecutively. The words include a first set of words in which each word has a length W, where W is the beat width. The words further include a second set of words in which each word has a length that is smaller or equal to W. The method further includes constructing a parity word of length W, wherein each bit in the parity word is a parity associated with a distinct word in the first and second set of words. The method further includes adding the parity word to the words to form the beat.
    Type: Application
    Filed: July 15, 2024
    Publication date: June 19, 2025
    Applicant: Micron Technology, Inc.
    Inventors: Marc SFORZIN, Paolo AMATO
  • Source address memory managment
    Patent number: 12333181
    Abstract: Methods, systems, and apparatuses related to source address memory management are described. For example, a controller can be coupled to a memory device to select a source block, a destination block, and a metadata block. The controller can store metadata indicative of an address of the source block in the metadata block. The controller can perform a memory management operation to transfer data from the source block to the destination block.
    Type: Grant
    Filed: March 8, 2024
    Date of Patent: June 17, 2025
    Assignee: Micron Techology, Inc.
    Inventors: Xiangang Luo, Jianmin Huang, Xiaolai Zhu
  • Adaptive pre-read management in multi-pass programming
    Patent number: 12334153
    Abstract: Exemplary methods, apparatuses, and systems include an adaptive pre-read manager for controlling pre-reads of the memory device. The adaptive pre-read manager receives a first set of data bits for programming to memory. The adaptive pre-read manager performing a first pass of programming including a first subset of data bits from the set of data bits. The adaptive pre-read manager compares a set of threshold operating differences to a set of differences between multiple operating conditions during the first pass of programming and current operating conditions. The adaptive pre-read manager performs an internal pre-read of the programmed first subset of data bits. The adaptive pre-read manager performs a second pass of programming using the internal pre-read and a second subset of data bits from the first set of data bits.
    Type: Grant
    Filed: September 9, 2022
    Date of Patent: June 17, 2025
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Kishore Kumar Muchherla, Huai-Yuan Tseng, Akira Goda, Dung V. Nguyen, Giovanni Maria Paolucci, James Fitzpatrick, Eric N. Lee, Dave Scott Ebsen, Tomoharu Tanaka
  • Memory sub-system LUN bypassing
    Patent number: 12332776
    Abstract: A method includes assigning a respective initial credit value to each LUN of a block stripe; performing an erase operation across the block stripe; reducing, in response to the erase operation, each respective initial credit value by a unit increment to provide a respective reduced credit value; refraining from programming to each LUN of the block stripe having a respective reduced credit value equal to zero; and programming to each LUN of the block stripe having a respective reduced credit value greater than zero.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: June 17, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Meng Wei
  • Zone-aware memory management in memory sub-systems
    Patent number: 12332804
    Abstract: Disclosed is a system including a memory device having a plurality of physical memory blocks and associated with a logical address space that comprises a plurality of zones, wherein each zone comprises a plurality of logical block addresses (LBAs), and a processing device, operatively coupled with the memory device, to perform operations of receiving a request to store data referenced by an LBA associated with a first zone of the plurality of zones, obtaining a version identifier of the first zone, obtaining erase values for a plurality of available physical memory blocks of the memory device, selecting, in view of the version identifier of the first zone and the erase values, a first physical memory block of the plurality of available physical memory blocks, mapping a next available LBA within the first zone to the first physical memory block, and storing the data in the first physical memory block.
    Type: Grant
    Filed: April 8, 2024
    Date of Patent: June 17, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Amit Bhardwaj
  • Single-level cell program-verify, latch-limited data recovery
    Patent number: 12334163
    Abstract: Control logic in a memory device identifies memory cells of a memory array configured as single-level cell (SLC) memory, where the memory cells include two or more memory cells programmed during a program phase and associated with a selected wordline of the memory array. The control logic further causes a program verify voltage to be applied to the selected wordline during a ganged SLC verify operation to be performed concurrently on the memory cells. In response to the memory cells failing to pass ganged SLC verify operation, the control logic further: copies first data, which is associated with a first memory cell, into the data recovery latch; causes a program verify operation to be performed separately on the first memory cell; and in response to the first memory cell reaching a program verify voltage, causes an inhibit of the first memory cell from further programming.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: June 17, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Eric N. Lee, Tomoko Ogura Iwasaki
  • Abrupt power loss management
    Patent number: 12333159
    Abstract: Implementations described herein relate to abrupt power loss management. In some implementations, a memory device may receive a peripheral component interconnect express reset (PERST) signal. The memory device may perform a write protect operation based on receiving the PERST signal. The memory device may initiate a reduced power consumption state of the memory device based on a completion of the write protect operation.
    Type: Grant
    Filed: November 16, 2023
    Date of Patent: June 17, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Marco Redaelli
  • Data integrity checks based on voltage distribution metrics
    Patent number: 12334166
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including determining a value of a data state metric of a memory page, wherein the data state metric value is reflective of a number of bit errors associated with the memory page; upon determining that the data state metric value satisfies a first threshold criterion, obtaining, from a neural network, a value of a voltage distribution metric associated with the page; and upon determining that the voltage distribution metric value satisfies a second threshold criterion, performing a media management operation with respect to a block associated with the page, wherein the media management operation comprises writing data stored at the block to a new block.
    Type: Grant
    Filed: September 27, 2023
    Date of Patent: June 17, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Michael Sheperek, Christopher M. Smitchger
  • Memory controller architecture
    Patent number: 12332803
    Abstract: An apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels are organized as a plurality of channel groups. The memory controller comprises a plurality of memory access request/response buffer sets, and each memory access request/response buffer set of the plurality of memory access request/response buffer sets corresponds to a different one of the plurality of channel groups.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: June 17, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Emanuele Confalonieri, Stephen S. Pawlowski, Patrick Estep
  • Row access strobe (RAS) clobber and row hammer failure mitigation
    Patent number: 12333022
    Abstract: There are provided systems and methods that include at least one memory that has a plurality of memory cells. The cells may be disposed in rows and columns. The device can further include a controller that is communicatively coupled to the at least one memory, and the controller may be configured by its hardware topology and its instruction set and/or by a communicatively coupled processor or higher-level system or subsystem to maintain data integrity in the at least one memory and/or to prevent or mitigate malicious access patterns that may compromise the at least one memory. The controller may be configured to execute a deterministic protocol in conjunction with or sequentially to a probabilistic protocol to achieve one or more of the above-noted functions.
    Type: Grant
    Filed: February 8, 2023
    Date of Patent: June 17, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Yang Lu, Markus H. Geiger, Nathaniel J. Meier
  • Link evaluation for a memory device
    Patent number: 12334172
    Abstract: Methods, systems, and devices for link evaluation for a memory device are described. A memory device may receive signaling over a channel and may identify logic values encoded into the signaling based on sampling the signaling against a reference voltage. The sampling may occur at a reference time within a sampling period. To evaluate a quality (e.g., margin of error) of the channel, the memory device may adjust the reference voltage, the reference time, or both, and either the memory device or the host device may determine whether the memory device is still able to correctly identify logic values encoded into signaling over the channel. In some cases, the channel quality may be evaluated during a refresh cycle or at another opportunistic time for the memory device.
    Type: Grant
    Filed: February 22, 2023
    Date of Patent: June 17, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Markus Balb, Thomas Hein, Heinz Hoenigschmid
  • Write timing compensation
    Patent number: 12334141
    Abstract: This document describes apparatuses and techniques for write timing compensation. In various aspects, a write timing compensator of a memory controller can apply a delay to data signals transmitted to a memory circuit based on various operating parameters, which may include voltage or latency information. In some cases, the memory controller or memory circuit powers components of write timing compensation circuitry using a dynamic power rail that scales with an operating voltage of the memory circuit. By so doing, the write timing compensator or compensation circuits may improve signal integrity of data signals communicated between the memory controller and the memory circuit at different frequencies and voltages.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: June 17, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Kang-Yong Kim, Keun Soo Song, Hyun Yoo Lee
  • Sacrificial strings in a memory device to detect read disturb
    Patent number: 12334142
    Abstract: Control logic in a memory device determines to initiate a string read operation on a first memory string of a plurality of memory strings in a block of a memory array, the block comprising a plurality of wordlines, wherein the first memory string is designated as a sacrificial string. The control logic further causes a read voltage to be applied to each of the plurality of wordlines concurrently and senses a level of current flowing through the sacrificial string while the read voltage is applied. In addition, the control logic identifies, based on the level of current flowing through the sacrificial string, whether a threshold level of read disturb has occurred on the block.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: June 17, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Violante Moschiano, Akira Goda, Jeffrey S. McNeil, Eric N. Lee
  • Reducing bit error rate in memory devices
    Patent number: 12333154
    Abstract: A processing device in a memory sub-system performs a first media scan operation with respect to a plurality of memory pages addressable by the ordinary wordline, wherein each page of the plurality of memory pages is contained by a respective management unit, and responsive to determining that a value of a data state metric of a memory page of the plurality of memory page addressable by the ordinary wordline satisfies a specified condition, performs a first media management operation with respect to a management unit containing the memory page.
    Type: Grant
    Filed: July 6, 2023
    Date of Patent: June 17, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Tingjun Xie, Yang Liu, Jiangli Zhu, Juane Li, Aaron Lee
  • Dynamic command extension for a memory sub-system
    Patent number: 12335374
    Abstract: A processing device is configured to process an initial set of command types. A command extension module and a digital signature are received. The digital signature is generated based on the command extension module using a private key of a key pair. The command extension module, once installed by the processing device, enables the processing device to process a new command type that is not included in the initial set of command types. The digital signature is verified using a public key of the key pair. Based on a successful verification of the digital signature, the command extension module is temporarily installed by loading the command extension module in a volatile memory device.
    Type: Grant
    Filed: December 14, 2023
    Date of Patent: June 17, 2025
    Assignee: Micron Technology, Inc.
    Inventors: James Ruane, Robert W. Strong