Patents Assigned to Micronics
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Patent number: 12347498Abstract: A data erase operation is performed on the memory system. The directed data erase operation performed on the memory system erases blocks of the memory device including blocks that are indicated as not including user data. In some embodiments, a data erase operation may be performed on a memory system to erase those groups of memory cells (e.g., blocks) indicated as not including user data. In some embodiments, a data erase operation may be performed on a memory system to erase those groups of memory cells (e.g., blocks) indicated as valid without erasing those groups of memory cells (e.g., blocks) indicated as invalid. In some embodiments, a data erase operation that can be performed on a memory system may obtain information associated with failing scenes of groups of memory cells (e.g., blocks) prior to obtaining the information, and erase the blocks (e.g., invalid blocks) subsequently.Type: GrantFiled: September 12, 2022Date of Patent: July 1, 2025Assignee: Micron Technology, Inc.Inventors: Kevin R. Brandt, Adam J. Hieb, Jonathan Tanguy, Preston A. Thomson
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Patent number: 12347519Abstract: Disclosed are methods for reading data from a storage buffer. One such method may include retrieving a first set of data during a first period of time. The method may also include delaying data retrieval during a second period of time after the first period of time. The method may include outputting at least a portion of the first set of data during the first period of time and the second period of time. The first period of time is substantially similar to the second period of time.Type: GrantFiled: October 14, 2022Date of Patent: July 1, 2025Assignee: Micron Technology, Inc.Inventor: Parthasarathy Gajapathy
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Patent number: 12346790Abstract: A state machine engine having a program buffer. The program buffer is configured to receive configuration data via a bus interface for configuring a state machine lattice. The state machine engine also includes a repair map buffer configured to provide repair map data to an external device via the bus interface. The state machine lattice includes multiple programmable elements. Each programmable element includes multiple memory cells configured to analyze data and to output a result of the analysis.Type: GrantFiled: February 15, 2023Date of Patent: July 1, 2025Assignee: Micron Technology, Inc.Inventors: Harold B Noyes, David R. Brown
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Patent number: 12347731Abstract: A semiconductor component includes a semiconductor substrate, conductive vias in the substrate having terminal portions, a polymer layer on the substrate and back side conductors formed by the terminal portions of the conductive vias embedded in the polymer layer. A stacked semiconductor component includes a plurality of components having aligned conductive vias in electrical communication with one another.Type: GrantFiled: January 5, 2024Date of Patent: July 1, 2025Assignee: Micron Technology, Inc.Inventors: Jin Li, Tongbi Jiang
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Patent number: 12347732Abstract: A method for mitigating crack propagation during manufacture of semiconductor dies, and associated systems and methods are disclosed herein. The method includes forming holes into a first side of a wafer substrate opposite a second side. The wafer substrate has active components at the second side. Each hole extends from the first side towards the second side an extend to an intermediate depth within the wafer substrate such that a bottom of the holes is spaced vertically apart from the active components on the second side. The holes are configured to inhibit cracks in the wafer substrate from propagating longitudinally across the wafer substrate. The method also includes backgrinding the first side of the wafer substrate to thin the wafer substrate after forming the holes. The method also includes dicing the wafer substrate after backgrinding to separate individual semiconductor dies from each other.Type: GrantFiled: April 24, 2023Date of Patent: July 1, 2025Assignee: Micron Technology, Inc.Inventors: Wei Yeeng Ng, Rajesh Balachandran, Frank Speetjens, Andrew L. Li, Sukhdeep Kaur, Sangeetha P. Komanduri
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Patent number: 12347713Abstract: Methods, apparatuses, and systems related to an apparatus with an alignment moat are described. An example apparatus includes a conductive material divided into first and second portions which include top surfaces connected to each other, respectively, a first spacer surrounding the first portion of the conductive material, and a second spacer surrounding the second portion of the conductive material, where the top surface of the first spacer and the top surface of the second spacer are indented from the top surface of the first portion and the top surface of the second portion, respectively, to define an alignment moat.Type: GrantFiled: May 18, 2022Date of Patent: July 1, 2025Assignee: Micron Technology, Inc.Inventor: Andrew D. Carswell
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Patent number: 12347511Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include computing an adjustment value of a threshold voltage offset associated with a block family of the memory device; determining that the adjustment value satisfies a threshold voltage criterion, wherein the threshold voltage criterion comprises a reference voltage level corresponding to known valley margins of the memory device; and updating the threshold voltage offset.Type: GrantFiled: January 26, 2024Date of Patent: July 1, 2025Assignee: Micron Technology, Inc.Inventor: Guang Shen
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Patent number: 12346090Abstract: Methods, devices, and systems related to process control in manufacturing are described. In an example, a method can include receiving data from a first process control device affixed to a first manufacturing tool of a first type, identifying one or more attributes of the data via a second processing resource of a second process control device affixed to a second manufacturing tool of a second type different from the first type, determining one or more settings for the second manufacturing tool via the second processing resource in response to identifying the one or more attributes of the data, and sending a command including the one or more settings to the second manufacturing tool from the second process control device.Type: GrantFiled: July 11, 2022Date of Patent: July 1, 2025Assignee: Micron Technology, Inc.Inventors: Fatma Arzum Simsek-Ege, Shruthi Kumara Vadivel, Deepti Verma, Anshika Sharma, Lavanya Sriram, Trupti D. Gawai
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Patent number: 12349346Abstract: Methods, systems, and devices for divider and contact formation for memory cells are described. In some examples, a protective mask (e.g., a photoresist layer) may be formed over existing circuit structures above a substrate. Contact structures may be exposed when the protective mask is removed. In some examples, the protective mask may be removed using a dry etching operation. In some examples, one or more additional etching operations may be performed to expose (and subsequently fabricate) additional circuit structures.Type: GrantFiled: April 28, 2022Date of Patent: July 1, 2025Assignee: Micron Technology, Inc.Inventor: Shuangqiang Luo
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Patent number: 12349371Abstract: Methods, systems, and devices for a vertical memory architecture are described. A memory device may include memory cells arranged in a three-dimensional vertical memory architecture. Each memory cell may include a storage element (e.g., a chalcogenide material), where a logic state may be programmed at the storage element based on a polarity of an applied voltage that exceeds a threshold voltage. The storage element may be coupled with a selection element and a conductive line. The selection element may be coupled with a bit line decoder and a word line decoder via vertical pillars. The selection element may selectively couple the storage element with the bit line decoder. In some examples, an activation voltage for the selection element may be less than a threshold voltage of the storage element.Type: GrantFiled: February 15, 2022Date of Patent: July 1, 2025Assignee: Micron Technology, Inc.Inventors: Agostino Pirovano, Fabio Pellizzer
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Patent number: 12348244Abstract: Methods, systems, and apparatuses detect and mitigate a stall condition in an iterative bit flipping decoder. A codeword is received and one or more of the bits in the codeword are flipped in each of multiple iterations of bit flipping decoding using a first set of bit flipping rules. Each of the iterations includes a determination of a syndrome weight. In response to determining a count of iterations in which the syndrome weight increased satisfies a threshold, one or more of the bits in the codeword are flipped in a subsequent iteration using a second set of bit flipping rules that differs from the first set of bit flipping rules.Type: GrantFiled: February 12, 2024Date of Patent: July 1, 2025Assignee: MICRON TECHNOLOGY, INC.Inventors: Mustafa N. Kaynak, Sivagnanam Parthasarathy
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Patent number: 12346263Abstract: A write request is determined to comprise at least a partial translation unit. A size of the partial translation unit is smaller than a size of a predefined translation unit. A first entry in a translation map is identified. The translation map maps a plurality of translation units to a plurality of physical blocks. The first entry identifies a first physical block corresponding to the predefined translation unit. A second entry in the translation map is created. The second entry identifies a second physical block. An association between the first entry and the second entry is created, such that the second entry corresponds to the predefined translation unit. A write operation is performed to write a set of data corresponding to the partial translation unit to the second physical block.Type: GrantFiled: August 12, 2022Date of Patent: July 1, 2025Assignee: Micron Technology, Inc.Inventor: Amit Bhardwaj
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Patent number: 12347737Abstract: This document discloses techniques, apparatuses, and systems for a semiconductor device with a porous air vent. The semiconductor device includes a semiconductor die mounted to a substrate at one or more contact pads. Underfill material is disposed between the semiconductor die and the substrate. The substrate includes a porous portion composed of a porous material. The porous material is such that air, but not the underfill material, may pass from an area between the semiconductor die and the substrate to an area below the substrate. As a result, air may pass through the porous portion during the underfill process and the underfill material may be retained.Type: GrantFiled: August 18, 2022Date of Patent: July 1, 2025Assignee: Micron Technology, Inc.Inventor: Jong Sik Paek
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Patent number: 12347797Abstract: According to one or more embodiments of the disclosure, an apparatus comprising a metal layer and a redistribution layer on the metal layer is provided. The redistribution layer includes an insulating layer, a via, and a redistribution metal layer. The via is in the insulating layer and has a rectangular shape in a plan view. The redistribution metal layer has a first thickness on a shorter side of the rectangular shape of the via and a second thickness on a longer side of the rectangular shape of the via. The second thickness is greater than the first thickness.Type: GrantFiled: September 26, 2022Date of Patent: July 1, 2025Assignee: Micron Technology, Inc.Inventors: Shigeru Sugioka, Keizo Kawakita
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Publication number: 20250210091Abstract: Some embodiments of the disclosure provide an apparatus comprising: a word line array including a plurality of word lines each extending through a memory mat in a first horizontal direction, the plurality of word lines including first and second word lines arranged adjacent to each other in a second horizontal direction; and a word line contact of the first word line, the word line contact separated from the second word line by a gap. The first and second word lines each have a first oxide film at a center area of the word line array in the memory mat. The first and second word lines each have a second oxide film at an edge area of the word line array outside the memory mat, the second oxide film having a thickness greater than a thickness of the first oxide film.Type: ApplicationFiled: July 22, 2024Publication date: June 26, 2025Applicant: MICRON TECHNOLOGY, INC.Inventors: Jun Ho Lee, Byung Yoon Kim
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Publication number: 20250212409Abstract: Some embodiments include an integrated assembly having a stack of alternating insulative levels and conductive levels. A pillar of channel material extends through the stack. Charge-storage-material-segments are adjacent to the conductive levels of the stack, and are between the channel material and the conductive levels. The charge-storage-material-segments contain one or more high-k oxides. At least a portion of each of the charge-storage-material-segments is vertically wider than the conductive levels. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: March 14, 2025Publication date: June 26, 2025Applicant: Micron Technology, Inc.Inventors: Kyubong Jung, Terry H. Kim
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Publication number: 20250210116Abstract: Memories might include an array of memory cells having a plurality of strings of series-connected memory cells and a controller configured to cause to memory to apply an erase pulse having a target voltage level and having an erase pulse flattop; for each suspend of a plurality of suspends initiated during the application of the erase pulse flattop, increase a value of the target voltage level; and resume applying the erase pulse having the target voltage level until initiation of any subsequent suspend of the plurality of suspends. Such controllers might further be configured to cause the memory to maintain the value of the target voltage level for each suspend of one or more additional suspends initiated during the application of the erase pulse flattop, and resume applying the erase pulse having the target voltage level until initiation of any subsequent suspend of the one or more additional suspends.Type: ApplicationFiled: December 10, 2024Publication date: June 26, 2025Applicant: MICRON TECHNOLOGY, INC.Inventors: Kannan Abinaya, Shyam Sunder Raghunathan, Dheeraj Srinivasan
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Patent number: 12340095Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including running sample data through each of a set of error-handling operations performed on data residing in a segment of the memory device in an existing order; and determining an optimized order of the set of error-handling operations based on probability data and latency data, wherein the probability data is associated with a result of running the sample data, and wherein the optimized order comprises an adjustment to an order of one or more error-handling operations of the set of error-handling operations in the existing order.Type: GrantFiled: May 9, 2024Date of Patent: June 24, 2025Assignee: Micron Technology, Inc.Inventors: Aswin Thiruvengadam, Vamsi Pavan Rayaprolu
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Patent number: 12340858Abstract: Apparatuses, systems, and methods for module level error correction. Multiple memory devices a packaged together in a memory module. The module includes a module error correction code (ECC) circuit which pools information multiple memory devices on the module. In an example read operation, multiple memory devices each provide a codeword which includes data bits and parity bits. The codewords may include data bits provided along a data bus and parity bits provided along a parity bus. The ECC circuit pools the codewords and detects errors in the pooled codewords.Type: GrantFiled: August 29, 2022Date of Patent: June 24, 2025Assignee: Micron Technology, Inc.Inventor: Sujeet Ayyapureddi
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Patent number: 12341128Abstract: Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with an opening extending therethrough. The assembly can include a stack of semiconductor dies attached to the substrate. The stack includes a first die attached to a front surface of the substrate, where the first die includes a first bond pad aligned with the opening. The stack also includes a second die attached to the first die such that an edge of the second die extends past a corresponding edge of the first die. The second die includes a second bond pad uncovered by the first die and aligned with the opening. A bond wire formed through the opening couples the first and second bond pads with a substrate bond pad on a back surface of the substrate.Type: GrantFiled: October 18, 2022Date of Patent: June 24, 2025Assignee: Micron Technology, Inc.Inventor: Jungbae Lee
