Abstract: A semiconductor die is provided, comprising a semiconductor substrate; a dielectric layer over the semiconductor substrate; a bond pad in the dielectric layer, the bond pad including an exposed top surface that is recessed with respect to a surface of the dielectric layer opposite to the semiconductor substrate; and a region of piezoelectric material in the dielectric layer, wherein the region is located proximate to the bond pad to supply thermal energy to the bond pad in response to exposing the piezoelectric material to an externally-applied field.

Abstract: Methods, systems, and devices for differential strobe fault indication are described. A memory device may be configured to indicate a fault using a read strobe signal. The read strobe signal may be a read data strobe (RDQS) signal, such as a true RDQS (RDQS_t) signal or a complement RDQS (RDQS_c) signal. In some examples, the memory device may indicate the fault based on a characteristic of the read strobe signal, such as a pattern of the read strobe signal, a voltage level of the read strobe signal, a difference between a first read strobe signal and a second read strobe signal, or any combination thereof. In some examples, a host device may indicate to the memory device which characteristic of the read strobe signal the memory device is to use to indicate the fault.

Abstract: Apparatuses, systems, and methods for access operations during a voltage transition. A memory may receive a system voltage and a clock signal from a controller. The controller may be used to time operations such as write operations however, an internal clock signal of the memory may be dependent on the voltage. The memory operates at a double data rate relative to the clock signal. During a transition period while the voltage changes between levels, the memory may switch to a transition mode where the memory operates at a single data rate.

Abstract: An example apparatus includes a first circuit configured to generate a first internal command signal in response to receiving an external command; a second circuit configured to receive the first internal command signal and a degradation control signal to generate a first mixed signal including a first internal command portion and a degradation control signal portion; a third circuit configured to delay the first mixed signal to generate a second mixed signal; and a fourth circuit coupled to the third circuit, the fourth circuit being configured to: receive the second mixed signal; start masking the degradation control signal portion of the second mixed signal at a first timing after the external command is received; and stop masking the degradation control signal portion of the second mixed signal at a second timing after the first internal command portion is generated.

Abstract: An example apparatus includes a dividing circuit configured to divide an original data strobe signal supplied synchronously with a set of write data to generate first to fourth data strobe signals having mutually different phase from one another, a first data latch circuit configured to latch one of the set of write data synchronously with the first data strobe signal, the first data latch circuit being configured to be reset responsive to a first reset signal; a second data latch circuit configured to latch another of the set of write data synchronously with the second data strobe signal, the second data latch circuit being configured to be reset responsive to a second reset signal; and a burst counter circuit configured to activate the first and second reset signals responsive to the third and fourth data strobe signals.

Abstract: An example apparatus includes a clock divider configured to divide an original clock signal to generate a first clock signal and a second clock signal having different phase from the first clock signal; a first clock path; a second clock path; and a control circuit configured to: in a first operation mode, supply at least one pulse of the first clock signal to the first clock path and at least one pulse of the second clock signal to the second clock path; and in a second operation mode, supply at least one pulse of one of the first and second clock signals to the first clock path and supply at least one pulse of one of the first and second clock signals to the second clock path.

Abstract: Apparatuses, systems, and methods for data timing alignment with fast alignment mode. A stacked memory device includes an interface die and a number of core die. The interface and the core die each have an adjustable delay circuit adjusted by an interface delay code or a respective core delay code. The delay codes are adjusted based on a measured phase difference along a replica path. In a default maintenance state, the delay codes may be adjusted based on an average of the phase differences over time. Each time the phase difference matches a previous phase difference, the interface die changes a count value associated with that core die. If one or more of the count values cross a threshold, a state machine of the interface die enters a different delay adjustment state where averaging is not used. This may allow for correction of systemic errors such as voltage drift.

Abstract: Methods, systems, and devices for block conversion to preserve memory capacity are described. A device may perform a quantity of one or more access operations on a block that includes a set of memory cells configured as single-level cells each of which is configured for storing multiple bits. After performing the quantity of one or more access operations on the block the device may convert the set of memory cells from single-level cells into multiple-level cells configured for storing multiple bits. The device may then determine a remaining quantity of access operations permitted to be performed on the block and operate the bloc based on the remaining quantity of access operations.

Abstract: An apparatus can include a memory device and a controller coupled thereto. The controller can be configured to maintain a logical-to-physical (L2P) table including logical block addresses (LBAs). The LBAs are organized as partitions of the L2P table. Each partition of the L2P table includes a respective subset of the LBAs. The controller can be configured to monitor, for each partition of the LBA, a quantity of read/modify/write (R/M/W) operations and a quantity of read operations performed on the memory device at the respective subset of the LBAs. The controller can be configured to for each partition of the L2P table and based on the quantities of R/M/W operations and read operations performed on the memory device at the respective subset of the LBAs, adjust a value of respective granularities of the L2P table.

Abstract: A method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.

Abstract: A memory device includes an array of memory cells configured as single-level cell memory and control logic operatively coupled to the array of memory cells. The control logic performs operations including: causing hardware initialization of a set of sub-blocks that are to be programmed within the array of memory cells; causing a first sub-block of the set of sub-blocks to be preconditioned for a program operation; causing multiple pages of data to be programmed to respective ones of the set of sub-blocks; and selectively causing a program verify to be performed on memory cells of the set of sub-blocks after programming the multiple pages of data.

Abstract: Apparatuses and methods including multiple read modes for reading data from a memory are described. An example apparatus includes a memory including a first read mode and a second read mode. The memory has a read operation for the first read mode including a first pre-access phase, an access phase, and a first post-access phase. The read operation for the second read mode includes a second pre-access phase, the access phase, and a second post-access phase. The read operation for either the first read mode or the second read mode is performed responsive to the memory receiving a read command. The second pre-access phase is different from the first pre-access phase, with the second pre-access phase having a shorter time than the first pre-access phase measured from receipt of the read command.

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory. The random access memory is configured to store input data from a sensor, parameters of a first portion of an Artificial Neural Network (ANN), instructions executable by the Deep Learning Accelerator to perform matrix computation of the first portion of the ANN, and data generated outside of the device according to a second portion of the ANN. The Deep Learning Accelerator may execute the instructions to generate, independent of the data from the second portion of the ANN, a first output based on the input data from the sensor and generate a second output based on a combination of the data from the sensor and the data from the second portion of the ANN.

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving, from a host system, a memory access command; executing the memory access command; identifying a characteristic associated with the memory access command; identifying a threshold period of time corresponding to the characteristic associated with the memory access command; determining that a period of time associated with the memory access command satisfies the threshold period of time; and responsive to determining that the period of time associated with the memory access command satisfies the threshold period of time, notifying the host system of completion of execution of the memory access command.

Abstract: Implementations described herein relate to emergency data storing operation selection. In some implementations, a memory device may be configured to receive a peripheral component interconnect power loss notification (PLN) signal and a peripheral component interconnect express reset (PERST) signal. The memory device may be configured to determine whether to initiate a first data storing operation or a second data storing operation based on the PERST signal state based on a falling edge of the PLN signal. The memory device may be configured to selectively initiate the first data storing operation or the second data storing operation. The first data storing operation may include storing data associated with the memory device prior to the memory device experiencing a power loss, and the second data storing operation may include storing data and metadata associated with the memory device prior to the memory device experiencing the power loss.

Abstract: A block storing corrupt data is detected. Based on detecting the block storing corrupt data, threshold voltage (VT) distribution data corresponding to the block is accessed. The VT distribution data comprises one or more VT distribution measurements corresponding to the block. The VT distribution data corresponding to the block is compared with reference VT distribution data. The reference VT distribution data comprises one or more reference VT distributions. Based on a result of the comparison, it is determined whether to perform one or more heroic data recovery processes on the block.

Abstract: The disclosed embodiments relate to an integrated circuit structure and methods of forming them in which photonic devices are formed on the back end of fabricating a CMOS semiconductor structure containing electronic devices. Doped regions associated with the photonic devices are formed using microwave annealing for dopant activation.

Abstract: A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including reading a first copy of data stored in a first set of memory cells comprising a first memory cell, determining whether a threshold voltage of the first memory cell is within a first range of threshold voltages, responsive to determining that the threshold voltage of the first memory cell is within the first range of threshold voltages, reading a second copy of the data stored in a second set of memory cells comprising a second memory cell, determining whether a threshold voltage of the second memory cell is within a second range of threshold voltages, and responsive to determining that the threshold voltage of the second memory cell is outside the second range, using the second copy of the data.

Abstract: Methods, systems, and devices for mitigating memory die misalignment are described. A memory system may receive a command to write data to a memory device including a memory die. The memory system may determine whether the data indicated by the command (e.g., a first set of data) satisfies a threshold size. If the first set of data satisfies the threshold size, the memory system may determine whether data currently in a write buffer aligns with a boundary of the memory die. For example, depending on the data currently in the buffer, adding the first set of data to the buffer may result in die misalignment for the first set of data. To mitigate die misalignment, the memory system may pad data (e.g., add dummy data) to the write buffer, such that the padding aligns the data with the die boundary.

Abstract: A memory device includes an ODT control circuit which provides an ODT pulse signal responsive to a command. The ODT control circuit compresses an ODT off latency added with a CRC bit based on a value of an ODT on latency. The compressed value of the ODT off latency added with a CRC bit is combined with the ODT on latency to generate a compressed ODT offset value. The duration of the ODT pulse signal is based on the compressed ODT offset value, a burst length, and an ODT pulse width parity. The combination of the compressed ODT offset and burst length is done along circuits of an even path or circuits of an odd path based on when the command was received. However, the compression and the generation of the ODT offset is shared between the even and odd paths.