Abstract: Systems, methods, and computer readable media for tracking memory deltas at a cache line granularity. The method includes receiving a base address for a physical memory region, receiving a list of empty log memory buffers associated with a delta logging session, and responsive to determining that a cache line associated with the physical memory region may be in a modified state, storing the modified cache line and metadata associated with the modified cache line in an active log memory buffer referenced by the list of empty log memory buffers. The method also includes determining that the active log memory buffer is full and appending a flag to the active log memory buffer, thereby marking the active log memory buffer as a full log memory buffer. The method also includes storing a list of full log memory buffers, wherein the list is visible to a host processor.

Abstract: Methods, systems, and devices for memory operations that support configuring a channel, such as a command/address (C/A) channel, are described. A configuration of a C/A channel may be dynamically adapted based on power saving considerations, control information execution latency, or both. Configuring a C/A channel may include determining a quantity of pins, or a quantity of cycles, both for communicating control information over the C/A channel. The quantity of pins may be determined based on previous control information transmissions, characteristics of a memory device, or predicted control information transmissions, or any combination thereof in some cases. The determined quantity of pins, quantity of cycles, or both may be explicitly or implicitly indicated to other devices (e.g., that use the C/A channel).

Abstract: Described apparatuses and methods relate to adaptive wordline refresh for a memory system that may support a nondeterministic protocol. To help manage power delivery networks in a memory system, a memory device can include logic that can stagger activation of multiple wordlines that are to be activated or refreshed approximately simultaneously. The logic circuitry can be coupled between wordlines that are to be activated and delay propagation of the activation signal. Thus, a first group of wordlines (e.g., “before” the logic circuitry) are activated by the signal, but activation of a second group of wordlines (e.g., “after” the logic circuitry), is delayed, reducing the peak current draw. Additional logic circuitries can be coupled between the wordlines to divide the wordlines into multiple groups, thereby staggering the activation of wordlines that are activated by a refresh command, which can reduce the peak current draw and power consumption.

Abstract: A method includes receiving first data, determining a number of programming operations performed on a plurality of flash memory cells subsequent to a most recent erase operation performed on the plurality of flash memory cells, encoding the first data to provide a first write-once memory (WOM) encoded data, and storing the first WOM encoded data, based at least in part on the determined number of programming operations, within a number of the plurality of flash memory cells.

Abstract: Memory devices may include a substrate supporting at least one semiconductor device thereon. The substrate may include an interface located proximate to an end of the substrate and sized, shaped, and configured to provide external electrical connection to the at least one semiconductor device. Hook-shaped engagement structures may be located proximate to, and laterally outward from, the interface, the engagement structures extending laterally beyond a longitudinal remainder of a lateral periphery of the substrate trailing the engagement structures. The end of the substrate may lack screw keep-outs. A carrier may include posts shaped, positioned, and configured to be positioned in throats of the hook-shaped engagement structures to secure the end of the substrate to the carrier. Sidewalls may extend longitudinally from a crossbar for placement along the remainder of the lateral periphery of the substrate.

Abstract: Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an integrated assembly includes a cell plate, a top electrode, and an insulator that separates the top electrode from bottom electrodes. The integrated assembly may include a first group of bottom electrodes that are coupled to the cell plate via a corresponding first group of leaker devices, wherein a first region between the first group of leaker includes the top electrode and the insulator. The integrated assembly may include a second group of bottom electrodes that are electrically coupled to the cell plate via a corresponding second group of leaker devices, wherein a second region between the second group of leaker devices does not include the top electrode and does not include the insulator. The first group of leaker devices and the second group of leaker devices have substantially identical electrical properties.

Abstract: Devices and techniques for continuous in-memory versioning are described herein. A memory subsystem includes a memory device configured to store a first data unit, a second data unit, and a third data unit, wherein the first, second, and third data units have a set of physical memory locations on the memory device, and metadata associated with the first, second, and third data units, the metadata including state information and a dirty commit timestamp; and a processing device, operatively coupled to the memory device, the processing device configured to: receive, from a host system, a first memory command associated with a logical memory address, the logical memory address mapped to the set of physical memory locations of the memory device; and in response to receiving the first memory command, perform a data operation on the first, second, or third data unit based on the state information and the dirty commit timestamp.

Abstract: In some implementations, a memory device may detect a read command associated with reading data stored by the memory device. The memory device may determine whether the read command is from a host device in communication with the memory device. The memory device may select, based on whether the read command is from the host device, one of a first voltage pattern or a second voltage pattern to be applied to memory cells of the memory device to execute the read command, wherein the first voltage pattern is selected if the read command is from the host device and the second voltage pattern is selected if the read command is not from the host device, wherein the second voltage pattern is different from the first voltage pattern. The memory device may execute the read command using a selected one of the first voltage pattern or the second voltage pattern.

Abstract: Systems, apparatuses, and methods related to a row hammer refresh operation are described herein. An example apparatus can include an array of memory cells of a memory device. The array of memory cells can include a plurality of dies and at least one of the plurality of dies is a row hammer die. The example apparatus can include a memory controller coupled to the array of memory cells. The memory controller can perform a number of operations on the array of memory cells. The memory controller can detect a quantity of accesses associated with the row hammer die and based on the number of operations performed. The memory controller can, in response to detection of a threshold quantity of accesses of a group of memory cells in the row hammer die, perform a refresh operation on a group of memory cells in an additional die of the plurality of dies.

Abstract: Described apparatuses and methods enable a system including at least one memory device to load different address scramble patterns on dies of the memory device. The address scramble patterns may include the logical-to-physical conversion of rows in the memory device or the memory dies. In aspects, the apparatuses and methods can change the address scrambles at different intervals, such as after a power reset or when the data stored on the memory device is invalid, not current, flushable, or erasable. The described aspects may reduce effectiveness of usage-based disturb attacks used by malicious actors to discover a layout of a type of particular memory device or memory die.

Abstract: Methods, apparatuses, and systems for in-or near-memory processing are described. Strings of bits (e.g., vectors) may be fetched and processed in logic of a memory device without involving a separate processing unit. Operations (e.g., arithmetic operations) may be performed on numbers stored in a bit-parallel way during a single sequence of clock cycles. Arithmetic may thus be performed in a single pass as numbers are bits of two or more strings of bits are fetched and without intermediate storage of the numbers. Vectors may be fetched (e.g., identified, transmitted, received) from one or more bit lines. Registers of a memory array may be used to write (e.g., store or temporarily store) results or ancillary bits (e.g., carry bits or carry flags) that facilitate arithmetic operations. Circuitry near, adjacent, or under the memory array may employ XOR or AND (or other) logic to fetch, organize, or operate on the data.

Abstract: Methods, systems, and devices for secure operating system update are described. A first message including a first value and a request associated with an operating system that is stored in a write-protected area of memory may be transmitted to a server. In response to the first message, a second message including data associated with the operating system, a second value corresponding to the first value, and a signature of the server may be received. The data associated with the operating system may be validated based on the signature of the server and a comparison of the second value and the first value. Based on validating the data associated with the operating system, the data associated with the operating system may be written to the write-protected area of memory.

Abstract: Systems and methods for a semiconductor device having a front-end-of-line interconnect structure are provided. The semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor or silicon substrate material and a front side, and a conducting material on the front side of the dielectric material. The conducting material may have a line portion and an interconnect structure electrically coupled to the line portion and separated from the front side of the substrate material by the dielectric material. The interconnect structure has a backside defining a contact surface. The semiconductor device may further include a semiconductor die proximate the front side of the dielectric material, an insulating material encasing at least a portion of the semiconductor die, and an opening through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.

Abstract: Methods, apparatuses, and systems related to calibrating memory circuitry according to externally provided reference voltage are described. A memory device may include a calibration control logic that at least isolates an internal reference voltage from an internal buffer. The internal buffer may receive and process the externally provided reference voltage instead of command-address signals for calibration purposes.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a data integrity check on a source set of memory cells, configured to store a first number of bits per memory cell, to obtain a data integrity metric value; responsive to determining that the data integrity metric value satisfies the threshold criterion, performing an error handling operation on the data stored on the source set of memory cells to generate corrected data; and causing the memory device to copy data the corrected data to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell, wherein the second number of bits per memory cells is greater than the first number of bits per memory cell.

Abstract: A semiconductor device includes first conductive lines extending in a first direction, second conductive lines extending in a second direction, memory cells disposed between the first conductive lines and the second conductive lines, each memory cell disposed at an intersection of a first conductive line and a second conductive line, and a passive material between the memory cells and at least one of the first conductive lines and the second conductive lines. Related semiconductor devices and electronic devices are disclosed.

Abstract: Methods, systems, and devices for maximum memory clock estimation procedures are described. For instance, a device, such as a host device, may truncate a value of a first parameter associated with a first duration for a clock coupled with a memory array to perform a clock cycle and may estimate a value of a second parameter that is inversely proportional to the truncated value of the first parameter. The device may determine a quantity of clock cycles associated with a maximum duration for accessing one or more memory cells of the memory array based on adjusting the second parameter. The device may access the one or more memory cells of the memory array based on the determined quantity of clock cycles associated with the maximum duration.

Abstract: A semiconductor device includes a first sensing stage configured to sense a voltage differential of a data signal and a reference signal and output a first amplified voltage differential, wherein the first amplified voltage differential includes a first voltage at a first output node and a second voltage at a second output node. The semiconductor device further includes a second sensing stage configured to sense the first amplified voltage differential and output a second amplified voltage differential, where the second amplified voltage differential includes a third voltage at a third output node and a fourth voltage at a fourth output node. A first power gating circuit is coupled to the third output node and a second power gating circuit is coupled to the fourth output node.

Abstract: A method includes performing a read operation of a first codeword including first hard data and generating an error vector using a reliability metric of the first hard data. The first hard data and error vector are stored in first and second portions of memory. A first corrected codeword is returned that combines the error vector and the hard data from the first and second portions of memory. A read operation of a second codeword is performed, including second hard data and soft information. The hard data and soft information are stored in the first and second portions of memory. A bit of second hard data is flipped responsive to comparing a reliability metric of the bit of the second hard data to a bit flipping threshold, wherein flipping the bit includes updating the second hard data. The updated second codeword is returned resulting from reading the portions of memory.

Abstract: A semiconductor die is provided, comprising a semiconductor substrate; a dielectric layer over the semiconductor substrate; a bond pad in the dielectric layer, the bond pad including an exposed top surface that is recessed with respect to a surface of the dielectric layer opposite to the semiconductor substrate; and a region of piezoelectric material in the dielectric layer, wherein the region is located proximate to the bond pad to supply thermal energy to the bond pad in response to exposing the piezoelectric material to an externally-applied field.