Abstract: A variable gain power amplifier includes a power amplifying unit and a signal generating unit. The power amplifying unit includes a control terminal, and a gain of the power amplifying unit is variable by a control signal provided through the control terminal. The signal generating unit generates the control signal to be provided to the control terminal. The signal generating unit includes a switching circuit to be turned on and off by a binary signal, a constant current source that generates a constant current, and a variable current source that generates a variable current. Also, the signal generating unit generates, when the switching circuit is on, a control signal of a magnitude that turns on the power amplifying unit and depends on a magnitude of a sum of the constant current and the variable current. When the switching circuit is off, the signal generating unit generates a control signal of a magnitude that turns off the power amplifying unit.

Abstract: A first RF receiving path and a second RF receiving path are activated selectively. An interstage filter is connected with the first RF receiving path and the second RF receiving path, and passes a prescribed frequency band of an RF signal output from an active RF receiving path. A frequency converter unit converts a signal output from the interstage filter into an IF signal. A bandwidth of the interstage filter corresponds to a center frequency of an RF signal to be received by the first RF receiving path. The second RF receiving path includes a center frequency shift unit that shifts a center frequency of a received RF signal so that it is included in a frequency band to pass through the interstage filter.

Abstract: A screen mask cleaning apparatus including an upper wiping sheet for cleaning the upper surface of a screen mask in which the upper wiping sheet is brought into contact only by its own weight with the upper surface of the screen mask, and a screen mask cleaning method performed by using the screen mask cleaning apparatus.

Abstract: A semiconductor memory device includes a plurality of memory cells 205 provided corresponding to nodes of a plurality of word lines (WLBk, WLBk+1) and a plurality of bit line pairs (D1, DB1, D1+1, DB1+1). And column selection lines (S1, S1+1) are provided corresponding to each of the bit line pairs. Each of the memory cell includes an inverter (INV3) receiving power from the column selection line, and having its input connected to the word line and its output connected to gates of access transistors. Only the access transistors of a memory cell whose word line and column selection line are simultaneously selected are turned on.

Abstract: A bus driver device is provided with a bus driver circuit connected to a bus line and a overvoltage protection section connected between the bus line and a power supply line. The overvoltage protection section has an overvoltage protection function for the bus line. Further, the bus driver device is provided with a switching circuit for on/off-controlling the overvoltage protection function based on a voltage of the bus line and a voltage of the power supply wiring.

Abstract: A signal transmission circuit having four lanes includes a constant voltage circuit to generate a constant voltage, a current supply circuit, and differential driver circuits respectively placed for the lanes. The current supply circuit receives a constant voltage from the constant voltage circuit and generates four currents having a value corresponding to a prescribed voltage-current conversion ratio and outputs them in parallel. The differential driver circuits respectively receive the currents output from the current supply circuit and output a voltage having an amplitude corresponding to the prescribed voltage-current conversion ratio. The current supply circuit includes a voltage divider circuit and an analog selector, which form a current supply control circuit capable of changing the voltage-current conversion ratio.

Abstract: A fuse used for redundancy function in a semiconductor device includes a pair of fuse terminals formed as a common layer with top interconnect lines by using a damascene technique, and a fuse element made of refractive metal and bridging the fuse terminals. The fuse element is formed as a common layer with the protective cover films covering the interconnect lines.

Abstract: In a multi-chip package having vertically stacked semiconductor integrated circuits (chips), a heat transmitting conductive plate (5) can be interposed between a lower layer semiconductor chip (3) and an upper layer semiconductor chip (4) and connected to a ground wiring of a substrate (2) through a bonding wire (9). A heating transmitting conductive plate (5) at the ground potential can block propagation of noise between the lower layer semiconductor chip (3) and upper layer semiconductor chip (4). Thus, the addition of noise to signals of an analog circuit in the upper layer semiconductor chip (4) can be avoided, reducing noise induced malfunctions. Furthermore, heat generated by the lower layer semiconductor chip (3) and upper layer semiconductor chip (4) can be transmitted through contact points with the heat transmitting conductive plate (5) for dissipation therefrom. This can improve heat dissipating capabilities of the semiconductor device (1) contributing to more stable operation.

Abstract: Wiring is routed to assure insulation between wiring traces in a semiconductor integrated circuit device. The device includes a first wiring trace to which a prescribed voltage is supplied; a second wiring trace that takes on a voltage that exceeds the prescribed voltage; and a third wiring trace that only takes on a voltage less than the prescribed voltage. Alternatively, the device includes a first wiring trace to which a prescribed voltage is supplied; a second wiring trace that takes on a voltage less than the prescribed voltage; and a third wiring trace that takes on a voltage equal to or greater than the prescribed voltage. The wiring traces are routed at a certain wiring space in such a manner that the first wiring trace is interposed between the second and third wiring traces. The first wiring trace for which the potential difference is known to be small beforehand is routed so as to always be adjacent to the second wiring trace.

Abstract: A fuse circuit in accordance with one embodiment of the present invention includes a first power supply line, a second power supply line, a current source connected between the first power supply line and an output terminal, a first transistor having a drain or a collector connected to the output terminal, the first transistor having a current supply capability or a current draw capability larger than that of the current source for the output terminal, a second transistor having a gate or a base connected in common with the gate or the base of the first transistor, a first resistive element and a fuse connected in series between the source or the emitter of either one of the first or second transistor and the second power supply line, and a second resistive element connected between the source or the emitter of the other one of the first or second transistor and the second power supply line.

Abstract: A semiconductor device comprises a plurality of unit cells, each comprising a vertical metal oxide semiconductor field effect transistor (MOSFET). The unit cell includes a first source region formed in a first base region, a second source region formed in the first base region and separated from the first source region, and a second base region formed in the first base region and disposed between the first and second source regions. The semiconductor device further comprises a trench gate formed in a vicinity of each of the plurality of unit cells. The second base region of an unit cell is separated from the second base region of an adjacent unit cell, and the first or second source region of an unit cell is separated from the first or second source region of an adjacent unit cell.

Abstract: In a semiconductor device including a bipolar transistor, a base region has a two layer structure including a first base region, and a second base region which is provided around the first base region and has a lower impurity density than that of the first base region and has a shallower depth than that of the first base region.

Abstract: An improved throughput can be presented, since an influence of the deterioration in crystallinity created in the epitaxial layer can be eliminated by a simple and easy method, and a semiconductor laser device having stabilized properties such as threshold current, slope efficiency, device life time and the like can be presented. A method for manufacturing a semiconductor laser device according to the present invention comprises: forming partially a diffraction grating on a surface of a semiconductor substrate or on a film on the surface of the semiconductor substrate; and forming a multiple-layered film by forming an epitaxial layer on a surface of the diffraction grating. The operation of forming the diffraction grating includes an operation of forming the diffraction grating so that a width of the diffraction grating in a direction that is orthogonal to a cavity direction of the semiconductor laser device is presented as a width equal to or longer than a sum of a mesa width and 30 ?m.

Abstract: Disclosed is a semiconductor device which has a circuit-forming region. The semiconductor device has a semiconductor substrate, a plurality of insulating interlayer films, a guard ring, and a first MIM capacitor. The insulating interlayer films, which are stacked one upon another, are provided over the semiconductor substrate. The guard ring is formed in the plurality of insulating interlayer films and surrounds the circuit-forming region. The guard ring is separated from an insulating interlayer film including a topmost interconnect. The MIM capacitor is provided between the guard ring and the insulating interlayer film including the topmost interconnect.

Abstract: Even in the case of a thin semiconductor chip, the semiconductor chip is delaminated from an adhesive sheet so as to prevent cracking. A pick-up apparatus 1 has a stage 100 on which a dicing sheet 13 is placed, a slider which comes into contact with a back surface of the dicing sheet 13 and moves horizontally, in plan view, with respect to a semiconductor chip 12, a slider housing portion which is formed in the stage 100 and houses the slider, and a suction mechanism 500 which is coupled to the stage 100 and suctions the slider housing portion. On the stage 100, the dicing sheet 13 is placed in a position where the semiconductor chip 12 is opposed to the slider housing portion. The slider is provided with a plurality of slits on a side where the slider comes into contact with the dicing sheet 13. The slit is in communication with the slider housing portion 102.

Abstract: The present invention provides a semiconductor device exhibiting an improved reliability. A semiconductor device comprises a semiconductor chip having an electrode on a surface thereof and a mounting substrate, and the electrode (aluminum electrode) of the semiconductor chip is coupled to the mounting substrate through a bump (solder bump 104). A plurality of diffusion barrier films (UBM 112) for preventing a diffusion of a material composing the bump is provided between the electrode and the bump, and the diffusion barrier film is formed to have a plurality of divided portions via spacings therebetween.

Abstract: A semiconductor device includes a pre-buffer for transferring a data signal on the basis of a first power supply voltage, a main buffer for amplifying and outputting the data signal transferred by the pre-buffer on the basis of a second power supply voltage different from the first power supply voltage, a switch unit for controlling a conductive state between the pre-buffer and the main buffer on the basis of a switch control signal, and a control circuit for generating the switch control signal for controlling the pre-buffer to set an output level of the pre-buffer to ground potential in accordance with transition of logical level of the switch control signal.

Abstract: In a visual inspection method and apparatus, a picture processing unit converts an original picture, obtained by taking a photograph of a BGA illuminated by a ring illuminator from above, by using a camera, and labels a binary picture obtained by this binary conversion. Then, it forms a circumscribing rectangle circumscribing an outer circumference of a labeling picture obtained by the labeling, and inverts a labeling picture within the formed rectangle, and removes a portion of a region formed by the outer circumference and the circumscribing rectangle in a picture obtained by the inversion, and then generates an inspection picture by adding a picture obtained by the removal to the labeling picture, and accordingly judges a pass or rejection of the inspection target sample based on the generated inspection picture. Thus, the inspection can be carried out at a high accuracy irrespectively of a low cost.

Abstract: Mechanical strength and moisture resistance of a multilayer interconnect structure is to be improved. A semiconductor device includes a circuit region and a seal ring region formed around the circuit region, on a semiconductor substrate. The seal ring region includes a plurality of interconnect layers including interconnect lines and a plurality of via layers including a plurality of slit vias stacked on one another, and a pitch between the slit vias in at least one of the via layers (lower or middle layer) is different from a pitch between the slit vias in other via layers (upper layer).

Abstract: Disclosed is a bolometer infrared imaging device including a plural number of readout circuits, each comprising a bias circuit that includes a bias transistor that supplies a constant voltage to a bolometer device, a bias cancellation circuit that includes a canceller transistor that removes offset current component of the bolometer device and an integrating operational amplifier that integrates the difference current between the current flowing in the bias transistor and that flowing in the canceller transistor. The bias circuit includes a source follower circuit that receives a first input voltage and supplies an output voltage to the gate of the bias transistor. The bias cancellation circuit includes a source follower circuit that receives a second input voltage and supplies an output voltage to the gate of the canceller transistor.