Abstract: Disclosed is a bolometer infrared imaging device including a plural number of readout circuits, each comprising a bias circuit that includes a bias transistor that supplies a constant voltage to a bolometer device, a bias cancellation circuit that includes a canceller transistor that removes offset current component of the bolometer device and an integrating operational amplifier that integrates the difference current between the current flowing in the bias transistor and that flowing in the canceller transistor. The bias circuit includes a source follower circuit that receives a first input voltage and supplies an output voltage to the gate of the bias transistor. The bias cancellation circuit includes a source follower circuit that receives a second input voltage and supplies an output voltage to the gate of the canceller transistor.

Abstract: A charge pump type booster circuit generates a positive or negative boosted output voltage by switching booster paths one by one. This charge pump type booster circuit includes a plurality of booster paths, each of the plurality of booster paths including at least one booster capacitor, wherein a number of the booster capacitor at each of the plurality of booster paths is different between one booster path and the other booster path. This makes it possible to suppress an increase in a number of an external capacitor for setting an output voltage of the booster circuit constant.

Abstract: The semiconductor device 1 has a semiconductor chip 10 (first semiconductor chip) and a semiconductor chip 20 (second semiconductor chip). The semiconductor chip 20 is formed on the semiconductor chip 10. The semiconductor chip 20 is constituted by comprising a semiconductor substrate 22. The semiconductor substrate 22, which is an SOI substrate, is constituted by comprising an insulating layer 34, and a silicon layer 36, which is provided on the insulating layer 34, including a circuit forming region A1. The insulating layer 34 functions as a protective film (a first protective film) covering a lower face (a face opposite to the semiconductor chip 10) of the circuit forming region A1. A protective film 38 (a second protective film) is provided on the semiconductor substrate 22. The protective film 38 covers a side face of the circuit forming region A1.

Abstract: A semiconductor device includes a capacitor with an MIM structure, by which the dimensional accuracy of the device is improved, and a stable capacitance value is given. The semiconductor device 100 includes: a semiconductor substrate 102; a capacitor forming region 130 in which an MIM capacitor is formed, which has an insulating interlayer 104 formed on the semiconductor substrate 102, a first electrode 110, and a second electrode 112, and the first electrode 110 and the second electrode 112 are arranged facing each other through the insulating interlayer 104; and a shielding region 132 which includes a plurality of shielding electrodes 114 formed in the outer edge of the capacitor forming region 130 and, at the same time, set at a predetermined potential in the same layer as that of the MIM capacitor on the semiconductor substrate 102, and shields the capacitor forming region 130 from other regions.

Abstract: There is provided a semiconductor apparatus which includes a substrate, a semiconductor chip mounted above the substrate, a first resin filled between the substrate and the semiconductor chip, and a second resin formed on the substrate and extending from a side surface of the semiconductor chip toward an outer edge of the substrate. The second resin extends from an intersection of an extension of the side surface of the semiconductor chip and the substrate toward the outer edge of the substrate so that a first stress generated on a contact surface between the first resin and the semiconductor chip and a second stress generated on a contact surface between the first resin or the second resin and the substrate balance out each other.

Abstract: A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.

Abstract: A semiconductor memory device adapted to burst transmission is provided for improving flexibility of data write operation. The semiconductor memory device is composed of a memory array, a set of write registers, and an input buffer designed to sequentially receive a series of write data during a burst cycle, and to write the write data into the associated write registers. The device also includes a write release register containing a set of write release flags associated with the write registers, respectively, and a write release register controller asserting the associated write release flags in response to the write data being written into the associated write registers. The device also contains a write amplifier designed to concurrently write the write data contained in the write registers associated with the asserted write release flags, selectively, when the burst cycle is aborted in response to a control signal.

Abstract: A semiconductor device includes a first pad, a second pad and a third pad. The first pad and the third pad are electrically connected to each other. The first pad and the second pad are used for bonding. The second pad and the third pad are used for probing. According to this structure, Small size semiconductor device having high reliability even after a probing test can be provided.

Abstract: An electrical fuse comprises: an interconnect to be cut; and a first terminal and a second terminal which are respectively provided at both ends of the interconnect to be cut. The interconnect to be cut comprises: a first orientation film which contains copper as a main component and is oriented in a (111) plane; and a second orientation film which contains copper as a main component and is oriented in a (511) plane. The second orientation film is provided inside the first orientation film over a width direction of the first orientation film, which is perpendicular to a direction from the first terminal toward the second terminal, so as to partition the first orientation film. Accordingly, it becomes possible to securely cut the electrical fuse whose constituent material is copper, and moreover, to maintain a satisfactory cut state of the electrical fuse after the cutting.

Abstract: In a class AB amplifier circuit, an input stage circuit includes a first differential pair configured to receive a differential signal and a first current mirror circuit connected with the first differential pair through a first node. A middle stage circuit includes a floating constant current source connected with the first node, a first transistor whose gate is applied with a bias voltage, and a first constant current source connected with the first node through the first transistor. A last stage circuit includes a first output stage transistor whose gate is connected with the first node and which controls a voltage of an output terminal. A first phase compensation capacitance has one end connected with a first connection node between the first constant current source and the first transistor and the other end connected with the output terminal.

Abstract: An input stage of a differential amplifier includes a differential pair formed by an N-channel MOS transistor MN1 having a gate connected to an INM and an N-channel MOS transistor MN2 having a gate connected to an INP, both having sources connected to each other, a constant current source connected to the sources of the MN1 and MN2, and a variable current source connected to the sources of the MN1 and MN2. A subsequent-stage processing circuit having an intermediate stage and an output stage includes a phase compensation capacitor and outputs an output responsive to a change in the differential inputs by charging and discharging the phase compensation capacitor through the constant current source. The variable current source turns ON when the change reaches a level causing a parasitic capacitor at the sources of the differential pair to be discharged, and supplies a current for discharging the parasitic capacitor.

Abstract: A lead frame is provided that includes a base metal, a plated layer provided on a part of the surface of the base metal, and a thermal history monitor portion that discolors under heat load applied thereto, provided at another part of the base metal surface. A method of manufacturing a semiconductor device includes an assembly process including mounting a semiconductor chip on the lead frame, performing a wire bonding process thereby connecting the semiconductor chip and the lead frame, and encapsulating with a resin the wire-bonded semiconductor chip and the lead frame, and then performing an appearance check after the assembly process to inspect whether the thermal history monitor portion has discolored under heat load applied through the assembly process, thereby deciding whether an abnormality has emerged through the thermal history.

Abstract: A gate line drive circuit includes: X level shift circuits configured to convert first address signals into second address signals; and a logic circuit configured to drive a selection gate line of N gate lines of a display unit based on the second address signals by supplying a first driving voltage to the selection gate line and by supplying a second driving voltage to non-selection gate lines of the N gate lines other than the selection gate line. X is an integer of 1 or more. N is equal to 2 raised to a power X. The first address signals includes X voltages each of which is a first voltage or a second voltage. The second address signals includes X driving voltages each of which is the first driving voltage or the second driving voltage.

Abstract: A substrate includes a base material, a first solder part disposed on a surface of the base material and used for connection to an electronic component, and a second solder part disposed on the surface of the base material and made of the same solder as that of the first solder part. The top surface of the first solder part is made to be a flat surface, and the maximum height of the second solder part from the surface of the base material is lower than the height of the flat surface of the first solder part from the surface of the base material. Thus, a substrate for which the kind of solder can be determined easily and with certainty, a device provided with this substrate, a method of manufacturing the substrate, and a determining method are provided.

Abstract: A semiconductor laser, which emits a laser beam from an edge surface of an active layer (5), is provided with a protective film (20), arranged on the edge surface from which the laser beam is emitted, and formed of a single-layer or a multilayer dielectric film. Hydrogen concentration distribution in the protective film (20) is approximately flat. The active layer (5) is formed of a group-III nitride semiconductor including Ga as a constituent element. The protective film (20) is formed of at least a first protective film (21) that is in direct contact with an edge surface of the active layer (5), and a second protective film (22) that is in contact with the first protective film (21). A ratio of hydrogen concentration of the first protective film (21) with respect to hydrogen concentration of the second protective film (22) is not less than 0.5 and not more than 2.

Abstract: Provided is a clock gating circuit which receives a first clock signal and controls an output of a second clock signal corresponding to the first clock signal in response to a control signal. The clock gating circuit includes: a first latch that latches a signal value of the control signal in synchronization with the first clock signal; an AND that receives the first clock signal and controls an output of the second clock signal in response to an output signal of the first latch; and a second latch that latches a signal value of the output signal of the first latch in synchronization with the first clock signal, and outputs a latched value. This enables execution of a scan test with a simple circuit configuration.

Abstract: A semiconductor apparatus has a light-receiving element. The light-receiving element has a photodiode unit having a shield film for removing noise, at least two test pads, and a shield film pseudo pattern which is formed by the same membranous type as the shield film and connected to the two test pads. The photodiode unit and the shield film pseudo pattern are integrated in one semiconductor chip. A resistance value of the shield film pseudo pattern is measured using the test pads connected to the shield film pseudo pattern. CMR of a photocoupler can be evaluated according to the correlation relationship between the measurement result and the sheet resistance of the shield film.

Abstract: A conventional layout of power supply protective element cannot sufficiently protect an internal circuit against a surge current that flows into a narrow branch line that branches off from a thick main wiring line. A semiconductor device according to an embodiment of the present invention includes a power supply protective element connected around a terminal; a main wiring line connected with a VCC pad or a GND pad; a branch line that branches off from the main wiring line and applies a power supply potential or a ground potential to a functional block of the semiconductor device; a branching portion at which the branch line branches off from the main wiring line; and an internal power supply protective element connected with the branch line.

Abstract: A controller driver includes a first compressor for compressing received image data to generate first compressed image data, a second compressor to generate second compressed image data, and an image memory capable of storing the second compressed image data of at least one frame. It also includes an overdrive processing unit for generating corrected image data where a tone value of the received image data is corrected from the first compressed image data or its expanded data and second compressed image data of one frame previous to the first compressed image data or its expanded data. The compression processing performed in the first compressor is the same as compression processing performed in the second compressor in compressing image data of one frame previous to the received image data.

Abstract: An image decoding apparatus includes an analyzing section and an image decoding section. The analyzing section determines a process quantity of a coded image data to each of a plurality of image decoding processes within a unit process time based on a parameter of the coded image data, prior to the plurality of image decoding processes. The image decoding section carries out each of the plurality of image decoding processes to the coded image data for the determined process quantity such that a decoded image data is generated from the coded image data.