Patents Assigned to NEC Electronics
  • Patent number: 7843226
    Abstract: A semiconductor integrated circuit device includes a column of first logic circuit cells arranged along a first side of a chip and a column of second logic circuit cells arranged along a second side orthogonal to the first side. At a corner part where the first side crosses the second side, a first test logic circuit cell is arranged to have its long side faced with a side of a cell at an end portion of the column of the first logic circuit cells and a second logic circuit cell is arranged to have its long side faced with a side of a cell at an end portion of the column of the second logic circuit cells. The first and the second test logic circuit cells are arranged so a that planar shapes thereof are symmetrical (mirror symmetrical) to each other with respect to a virtual line intermediate between the oblique sides arranged opposite to each other.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: November 30, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Takayuki Momose
  • Patent number: 7843229
    Abstract: Disclosed is a signal output circuit comprising: a first transistor of an emitter follower configuration, which receives an input signal; a second transistor of an emitter follower configuration, which receives the input signal, and has an output connected to an external load (106); a comparator circuit which has an input pair connected via resistors to emitters of the first and the second transistors; a first current mirror circuit which has an input connected to an output of a first current source transistor and an output connected to an emitter of the first transistor; and a second current mirror circuit which has an input connected to a connection node of an output of a second current source transistor and an output of the comparator circuit, and has an output connected to an emitter of the second transistor.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: November 30, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Kenji Kimura, Masanori Sato
  • Patent number: 7842609
    Abstract: A hole is formed in an insulating layer. A semiconductor substrate is heated at a temperature of equal to or more than 330° C. and equal to or less than 400° C. Tungsten-containing gas and at least one of B2H6 gas and SiH4 gas are introduced into a reaction chamber to thereby form a first tungsten layer. Subsequently, at least one of H2 gas and inert gas is introduced into the reaction chamber, the temperature of the semiconductor substrate is raised to equal to or more than 370° C. and equal to or less than 410° C. with 30 or more seconds, and tungsten-containing gas is introduced into the reaction chamber to thereby form a second tungsten layer on the first tungsten layer.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: November 30, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Atsushi Kariya
  • Patent number: 7843262
    Abstract: Disclosed a power amplifier including a main amplifier with class bias AB and a peak amplifier with class C bias. A quarter-wave length transmission line having a length equal to one-fourth of the wave-length of a fundamental frequency is connected to an output side of the peak amplifier. Outputs of the main amplifier and the peak amplifier are combined. An envelope amplifier that modulates the drain bias voltage in accordance with an envelope of the modulation wave input signal and an envelope detector are provided as a drain-bias circuit for the main amplifier (FIG. 1).
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: November 30, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Isao Takenaka
  • Patent number: 7842979
    Abstract: A solid-state imaging device includes an N-type semiconductor substrate, an N-type impurity region provided in the surficial portion of the N-type semiconductor substrate, a photo-electric conversion unit formed in the N-type impurity region, a charge accumulation unit formed in the N-type impurity region so as to contact with the photo-electric conversion unit, and temporarily accumulating charge generated in the photo-electric conversion unit, a charge hold region (barrier unit) formed in the N-type impurity region so as to contact with the charge accumulation unit, and allowing the charge accumulation unit to accumulate the charge, and a charge accumulating electrode provided to the charge accumulation unit. The charge accumulation unit and the charge hold region are formed to be N?-type.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: November 30, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Hiroyoshi Kudou, Satoshi Uchiya, Junichi Yamamoto, Fumiaki Futamura
  • Patent number: 7844873
    Abstract: A fault location estimation system includes single-fault-assumed diagnostic unit nodes; error-observation node basis candidate classification unit; inclusion fault candidate group selection unit; inter-pattern overlapping unit; and multiple-fault simulation checking unit.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: November 30, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Yukihisa Funatsu
  • Patent number: 7842576
    Abstract: The invention provides a method of manufacturing a semiconductor device including a non-volatile memory with high yield, and a semiconductor device manufactured by the method. A method of manufacturing a semiconductor device includes a process of forming a second side wall such that the width of the second side wall, which is formed on the side of a portion of a second gate electrode that does not face dummy gates on a drain forming region side, in a gate length direction is larger than that of the second side wall, which is formed on the side of the second gate electrode on a source forming region side, in the gate length direction, in a non-volatile memory forming region.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: November 30, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Yoshitaka Kubota
  • Patent number: 7843214
    Abstract: A standard cell includes an input terminal, an output terminal, first and second inverters coupled in series between the input and output terminals, the first inverter including a first transistor of a first conductivity type and a second transistor of a second conductivity type, the first transistor being coupled between a first power source terminal and a first node, and the second transistor being coupled between a second node and a second power source terminal, and a plurality of resistance elements which are used to provide a conductivity path between the first and second nodes, in order to adjust a duty ratio of a signal which passes the standard cell.
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: November 30, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Kyoka Tatsumi
  • Patent number: 7841903
    Abstract: An adaptor according to an embodiment of the present invention includes: a power supply line to be connected to an external power supply; a first connector including a plurality of terminals; and a second connector including a first terminal connected to at least one of the plurality of terminals of the first connector and a second terminal connected to the power supply line. The adaptor realizes the connection between an external device and a wireless USB module.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: November 30, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Shinya Saito
  • Patent number: 7843008
    Abstract: A semiconductor device capable of dissipating heat, which has been produced in an ESD protection element, to the exterior of the device rapidly and efficiently includes an ESD protection element having a drain region, a source region and a gate electrode, and a thermal diffusion portion. The thermal diffusion portion, which has been formed on the drain region, has a metal layer electrically connected to a pad, and contacts connecting the drain region and metal layer. The metal layer has a first wiring trace extending along the gate electrode, and second wiring traces intersecting the first wiring trace perpendicularly. The contacts are connected to intersections between the first wiring trace and the second wiring traces. Heat that has been produced at a pn-junction of the ESD protection element and transferred through a contact is diffused simultaneously in three directions through the first wiring trace and second wiring trace in the metal layer and is released into the pad.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: November 30, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Mototsugu Okushima
  • Patent number: 7843372
    Abstract: In an mode of this invention, a digital/analog conversion circuit, includes: a digital/analog conversion portion which outputs a first current according to an input digital signal; and a first current mirror circuit which generates a mirror current according to the first current and outputs the mirror current as an analog signal, the digital/analog conversion circuit converting the digital signal into the analog signal, and further including: a second current mirror circuit, which generates a first mirror current according to the first current; and a third current mirror circuit, which is connected to a reference voltage, and to which the first mirror current is input, and which generates a second mirror current equal to the first current, according to the first mirror current, between the digital/analog conversion portion and the second current mirror circuit.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: November 30, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Takahiro Kawano
  • Publication number: 20100295584
    Abstract: A PLL circuit includes a polyphase reference clock output circuit that outputs reference clocks, a polyphase frequency divider circuit that outputs divided clocks, which is obtained by dividing frequencies of the reference clocks, a selection switch circuit that selects one of the reference clocks or one of the divided clocks, and outputs the selected clock as a selected clock, a digital VCO that uses the selected clock as an operating clock, and outputs delay amount data indicating a phase difference between an output clock and an ideal phase, where the output clock has a frequency that fluctuates according to a value of frequency control input data, and the ideal phase is calculated according to the output clock and the value of the frequency control input data, and a selection circuit that selects and outputs the output clock synchronized with the divided clocks according to the delay amount data.
    Type: Application
    Filed: May 5, 2010
    Publication date: November 25, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Masaki SANO
  • Publication number: 20100295530
    Abstract: A power supply voltage control circuit controls power supply voltage supplied to a target circuit that performs certain signal processing. The power supply voltage control circuit includes a control signal generation circuit that selectively generates first and second control signals when the power supply voltage supplied to the target circuit is increased from a first power supply voltage to a second power supply voltage, the second power supply voltage being higher than the first power supply voltage, and a power supply circuit that increases the power supply voltage toward a voltage level of the second power supply voltage based on the first control signal, or increases the power supply voltage to a voltage level higher than the second power supply voltage first and subsequently decreases the power supply voltage to the second power supply voltage based on the second control signal.
    Type: Application
    Filed: April 29, 2010
    Publication date: November 25, 2010
    Applicant: NEC Electronics Corporation
    Inventors: Yoshifumi Ikenaga, Masahiro Nomura
  • Publication number: 20100296069
    Abstract: There is provided a pattern division method to form crowded patterns accurately on a substrate includes acquiring a mask pattern, dividing a predetermine area into a plurality of areas to prepare a division pattern in which the plurality of the areas are classified into first and second groups, generating a reduced mask pattern by reducing each of two or more patterns laid out in the object mask pattern substantially toward the center of the particular pattern, overlapping the division pattern with the reduced mask pattern and extracting the reduced patterns overlapped with the area classified as the first group of the division pattern to generate a first reduced mask pattern, and restoring the reduced patterns laid out in the first reduced mask pattern to the original size before generation of the reduced mask pattern.
    Type: Application
    Filed: May 13, 2010
    Publication date: November 25, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Seiji Matsuura
  • Patent number: 7839714
    Abstract: A non-volatile semiconductor storage device, includes a memory array including memory cells, a plurality of word lines installed in the memory array, a sub-decoder including a pull-up power line, a pull-down power line and a plurality of drivers, a pre-decoder coupled to the sub-decoder, and generating a pre-decode signal; and a main decoder coupled to the sub-decoder, and generating a main decode signal. A potential of the pull-up power line and a potential of the pull-down power line are controlled in response to the main decode signal. The plurality of drivers drives the plurality of word lines in response to the pre-decode signal.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: November 23, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hiroshi Sugawara
  • Patent number: 7840922
    Abstract: The semiconductor design support apparatus relating to the layout verification. For executing layout verification in high accuracy, the apparatus includes a unit for generating a recognition pattern in a region having a first axis of symmetry and a second axis of symmetry orthogonal to the first axis. The recognition pattern is asymmetric to both first and second axes. The layout execution unit determines the layout of a macrocell including the recognition pattern to generate layout pattern data. The layout verification unit read the pattern data of the recognition pattern included in the macrocell based on the layout pattern data and verify the arrangement direction of the macrocell based on the recognition pattern.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: November 23, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Fumiko Hino
  • Patent number: 7838779
    Abstract: A wiring board in which lower-layer wiring composed of a wiring body and an etching barrier layer is formed in a concave portion formed on one face of a board-insulating film, upper-layer wiring is formed on the other face of the board-insulating film, and the upper-layer wiring and the wiring body of the lower-layer wiring are connected to each other through a via hole formed in the board-insulating film. The via hole is barrel-shaped, bell-shaped, or bellows-shaped.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: November 23, 2010
    Assignees: NEC Corporation, NEC Electronics Corporation
    Inventors: Shintaro Yamamichi, Katsumi Kikuchi, Hideya Murai, Takuo Funaya, Takehiko Maeda, Kenta Ogawa, Jun Tsukano, Hirokazu Honda
  • Patent number: 7838408
    Abstract: A process margin of an interconnect is to be expanded, to minimize the impact of vibration generated during a scanning motion of a scanning type exposure equipment. In a semiconductor device, the interconnect handling a greater amount of data (frequently used interconnect) is disposed in a same orientation such that the longitudinal direction of the interconnects is aligned with a scanning direction of a scanning type exposure equipment, in an interconnect layer that includes a narrowest interconnect or a narrowest spacing between the interconnects. Aligning thus the direction of the vibration with the longitudinal direction of the pattern can minimize the positional deviation due to the vibration.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: November 23, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Yoshihisa Matsubara, Hiromasa Kobayashi
  • Patent number: 7838961
    Abstract: A semiconductor device includes a semiconductor substrate having trenches extending thereinto. A trench type insulating film fills the trenches. The trench type insulating film includes a first and second insulating film and is laminated in a portion of the trenches.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: November 23, 2010
    Assignee: Nec Electronics Corporation
    Inventors: Kenji Saitou, Kenichi Hidaka
  • Patent number: 7839205
    Abstract: A step-down circuit is connected between a power supply node for supplying a supply voltage and an internal power supply line for supplying a power to the object circuit and steps-down the supply voltage, and supplies the stepped-down voltage to the object circuit through the internal power supply line. The step-down circuit includes a comparison circuit that compares a reference voltage with the voltage of the internal power supply line, and a driver that adjusts a current flowing between the internal power supply line and the power supply node according to the comparison result of the comparison circuit. The activity level of the driver is controlled so as to rise in a predetermined rising period synchronously with an activated operation of the object circuit and to fall in a predetermined falling period that comes after the rising period.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: November 23, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Atsunori Hirobe