Abstract: A method includes providing a memory unit in a computing device already including a number of processors communicatively coupled to a memory through a system bus, and providing a non-system bus based dedicated channel between the number of processors and the memory unit. The method also includes rendering a different video frame and/or a surface on each processor of the number of processors, and leveraging the memory unit to store a video frame and/or a surface rendered on a processor therein through the non-system bus based dedicated channel. Further, the method includes copying, to other processors, the stored video frame and/or the surface rendered on the processor from the memory unit through the non-system bus based dedicated channel, and scanning out, through the number of processors, the video frame and/or the surface rendered on the processor following the copying to enable display thereof on a corresponding number of displays.

Abstract: A system, method, and computer program product are provided for remedying a charging error. In use, a battery and a battery charger are identified. Additionally, an error associated with the charging of the battery by the battery charger is detected. Further, the error is remedied.

Abstract: Compiler techniques for inline parallelism and re-targetable parallel runtime execution of logic iterators enables selection thereof from the source code or dynamically during the object code execution.

Abstract: A system, method, and computer program product are provided for compiling a computer program comprising arithmetic operations having different requirements with respect to numeric dynamic range, numeric resolution, or any combination thereof. The method comprises generating a transformed graph representation of the computer program by applying propagation rules that provide for relaxed numeric requirements, where applicable, and generating output code based on the transformed graph representation. Relaxing numeric requirements, such as dynamic range and resolution requirements, may advantageously lower power consumption during execution of the computer program.

Abstract: A system, method, and computer program product are provided for GPU demand paging. In operation, input data is addressed in terms of a virtual address space. Additionally, the input data is organized into one or more pages of data. Further, the input data organized as the one or more pages of data is at least temporarily stored in a physical cache. In addition, access to the input data in the physical cache is facilitated.

Abstract: Provided is an antenna. In one aspect, the antenna includes a feed element having a first feed element end and a second feed element end, the first feed element end configured to electrically connect to a positive terminal of a transmission line. The antenna, in this aspect, further includes a loop antenna element having a first loop antenna element end and a second loop antenna element end, wherein the first loop antenna element end is coupled to the second feed element end and the second loop antenna element end is configured to electrically connect to a negative terminal of the transmission line. The antenna, of this aspect, further includes a monopole antenna element having a first monopole antenna element end and a second monopole antenna element end, wherein the first monopole antenna element end is coupled to the second feed element end.

Abstract: Methods are provided to perform area summation of various subsections of data values in a regular input array of one or several dimensions and varying sizes. The summation is achieved by adding up values from a ripmap of partial sums, where the partial sums are computed from the input array using a binary reduction method. According to such embodiments, the generation of the ripmap of partial sums will employ several binary reduction stages. Within each stage, a reduction operator is used that adds two elements along the respective direction. This is repeated until the output is only one element wide in the respective direction. The addresses of partial sums in the ripmap may subsequently be computed using a binary analysis of the target subsections in order to choose those partial sum values for a desired area that results in the desired area sum using an optimal number of data fetches.

Abstract: A system and method are provided for controlling a soft-switched modified buck regulator circuit. A voltage (Vx) across or a current through a pull-down switching mechanism within the modified buck regulator circuit is sensed when the pull-down switching mechanism is enabled, where the pull-down switching mechanism is coupled to an upstream end of an inductor and is coupled in parallel with a capacitor. A target time when the pull-down switching mechanism will be disabled (tlf) is computed and the pull-down transistor is disabled at the computed target time.

Abstract: A system, method, and computer program product enable compression with programmable sample locations, where the compression is a function of the programmable sample locations. The method includes the steps of storing a first value specifying a programmed sample location within a pixel in a sample pattern table and storing, in a memory, geometric surface parameters corresponding to a first attribute at the programmed sample location within a first pixel of a display surface. An instruction to store a second value specifying the programmed sample location within the pixel in the sample pattern table is received. The attribute is reconstructed based on the geometric surface parameters and the first value.

Abstract: A method includes receiving, through a processor of a data processing device communicatively coupled to a memory, data related to a dimensional parameter of a display unit and/or a distance between a user and the display unit, and determining, through the processor, a comfortable range of perception of a sub-portion of three -dimensional (3D) video data on the display unit based on the dimensional parameter of the display unit and/or the distance between the user and the display unit. The method also includes adjusting, through the processor, a disparity between one or more sub -portion(s) of the 3D video data corresponding to perception of the sub-portion by a left eye of the user and one or more sub-portion(s) of the 3D video data corresponding to perception of the sub-portion by a right eye of the user such that the sub-portion is mapped within the determined comfortable range of perception.

Abstract: An enhanced fuseless fuse structure is provided herein. Additionally, an IC with an enhanced fuseless fuse structure, a data structure that can be used with this structure and a method of manufacturing an IC are disclosed herein. In one embodiment, the IC includes: (1) a fuse wrapper configured to decode fuseless fuse data for controlling the fuses, (2) JTAG registers configured to store fuse register values in designated blocks, wherein the fuse register values and the designated blocks are determined from the fuseless fuse data and (3) options registers configurable by software to store fuse override data for modifying the fuse register values.

Abstract: A multimedia framework includes a monolithic multimedia component to include a specific interface provided by the multimedia framework, and a component control unit layer to serve as a point of control of an application, and to control a data flow through the monolithic multimedia component. When the application queries the component control unit layer for the specific interface, the specific interface passes a pointer thereof that signifies a role required by the application matching a role identified by the multimedia framework for the monolithic multimedia component to the application. A command from the application is transmitted to a tunnel of a multimedia stack interfaced with the monolithic multimedia component to ensure that the same monolithic multimedia component serves as a source component, one or more transform component(s) and/or a renderer. The application is unaware of the multi-tasking associated with the monolithic multimedia component.

Abstract: A method for processing a function with a plurality of execution spaces is disclosed. The method comprises creating an internal compiler representation for the function. Creating the internal compiler representation comprises copying substantially all lexical tokens corresponding to a body of the function. Further, the creating comprises inserting the lexical tokens into a plurality of conditional if-statements, wherein a conditional if-statement is generated for each corresponding execution space of said plurality of execution spaces, and wherein each conditional if-statement determines which execution space the function is executing in. During compilation, the method finally comprises performing overload resolution at a call site of an overloaded function by checking for compatibility with a first execution space specified by one of the plurality of conditional if-statements, wherein the overloaded function is called within the body of the function.

Abstract: 3D display device, 3D display system and method for displaying 3D images are disclosed in the present invention. The 3D display device comprises: a display screen; a backlight means including a pulse light source; and a drive means used to receive video signals which are based on a standard video transmission protocol, so as to control the display screen to display 3D images according to the video signals, and control the pulse light source to emit a backlight pulse in the form of pulse during a vertical blank of each frame period of the video signals, wherein the duration of the backlight pulse is shorter than that of the vertical blank. The degrading of light is avoided in the 3D display device and the efficiency of the backlight can achieve almost 100%.

Abstract: A system for, and method of, pixel data compression and a smartphone incorporating the system or the method. In one embodiment, the system includes: (1) a differential pulse code modulation encoder operable differentially to compress the two pixel values losslessly to yield two losslessly compressed pixel values and (2) an entropy encoder coupled to the differential pulse code modulation encoder and configured to receive and entropy-encode the losslessly compressed pixel values using a tiered technique to yield entropy-encoded, losslessly compressed pixel values. values using a tiered technique to yield Huffman-encoded, losslessly compressed pixel values.

Abstract: Embodiments of the present invention utilize an attachable lens board that can be secured to the back of a mobile device and placed in a position that is proximate to the built-in camera lens associated with the camera system of the mobile device. As such, the lens board can be positioned to accurately align several different auxiliary camera lenses, each installed within various camera lens receivers formed within the lens board, with the built-in camera lens for focusing and/or image capture. Additionally, embodiments of present invention can include circuitry within the lens board that can be used to identify the types of lenses currently installed within each camera lens receiver. In this manner, embodiments of the present invention can correct possible optical imperfections of resultant images produced by the combination of the built-in camera lens and auxiliary lens selected for focusing and/or image capture by the user.

Abstract: An apparatus including a receiver coupled to receive an input signal from a communication link and operable to employ decision feedback equalization to the input signal of the communication link and generate an edge sample signal. The apparatus also includes a timing recovery module coupled to the receiver and operable to receive the edge sample signal and use the edge sample signal to generate a data sampling phase signal, wherein the edge sample signal influences a settling point of the data sampling phase signal.

Abstract: A method for allocating registers within a processing unit. A compiler assigns a plurality of instructions to a plurality of processing clusters. Each instruction is configured to access a first virtual register within a live range. The compiler determines which processing cluster in the plurality of processing clusters is an owner cluster for the first virtual register within the live range. The compiler configures a first instruction included in the plurality of instructions to access a first global virtual register.

Abstract: A system, method, and computer program product are provided for evaluating an integral utilizing a low discrepancy sequence. In use, a low discrepancy sequence that includes at least one component that is a (0,1)-sequence in base b is determined. Additionally, an integral is evaluated, utilizing the low discrepancy sequence.

Abstract: A system, method, and computer program product enable compression with programmable sample locations, where the compression is a function of the programmable sample locations. The method includes the steps of storing a first value specifying a programmed sample location within a pixel in a first sample pattern table that is associated with a first display surface and storing, in a memory, geometric surface parameters corresponding to a first attribute at the programmed sample location within a first pixel of the first display surface. A second value specifying the programmed sample location within the pixel in a second sample pattern table that is associated with a second display surface is also stored and the first attribute is reconstructed based on the geometric surface parameters and the first value.