Abstract: Methods and apparatus for debugging finite state machine are disclosed. The method includes implementing a debug logic circuit and connecting the debug logic circuit to a system on chip (SoC) voltage source. The method includes operating a finite state machine that sequences the SoC from a low power state to a next low power state and generating respective output signals corresponding to the low power states and wherein the finite state machine is connected to Always On voltage source. The method includes masking the output signals to generate respective masked output signals, and applying the masked output signals to SoC circuit elements to prevent from transitioning into low power states and hence keeping the debug logic circuitry alive. The method includes debugging the finite state machine in the lowest power state by the debug logic circuit.

Abstract: One embodiment of the present invention sets forth a technique for coalescing memory barrier operations across multiple parallel threads. Memory barrier requests from a given parallel thread processing unit are coalesced to reduce the impact to the rest of the system. Additionally, memory barrier requests may specify a level of a set of threads with respect to which the memory transactions are committed. For example, a first type of memory barrier instruction may commit the memory transactions to a level of a set of cooperating threads that share an L1 (level one) cache. A second type of memory barrier instruction may commit the memory transactions to a level of a set of threads sharing a global memory. Finally, a third type of memory barrier instruction may commit the memory transactions to a system level of all threads sharing all system memories. The latency required to execute the memory barrier instruction varies based on the type of memory barrier instruction.

Abstract: A system and method are provided for refreshing a dynamic memory. A first region of a memory is refreshed at a first refresh rate and a second region of the memory is refreshed at a second refresh rate that is different than the first refresh rate. A memory controller is configured to refresh the first region of a memory at the first refresh rate and refresh the second region of the memory at the second refresh rate.

Abstract: A tile shader for screen space of a graphics pipeline, a method of rendering graphics and a graphics processing unit are disclosed. In one embodiment, the tile shader includes: (1) an input interface configured to receive a tile of pixels for processing and (2) a tile processor configured to perform tile-level processing of the pixels.

Abstract: A portable function-expanding device for an electronic device is provided which comprises: a housing with a plurality of accommodating slots provided on an upper surface thereof for accommodating electronic devices respectively, wherein a function-expanding interface is provided in each of the accommodating slots for being connected with a function interface of the electronic device accommodated therein; and a function means located in the housing and connected with the function-expanding interface to fulfill the function-expanding of the corresponding electronic device. The portable function-expanding device for an electronic device fulfills the function-expanding of the corresponding electronic device conveniently. That is, the function-expanding is fulfilled conveniently as required by just inserting the electronic device into the corresponding accommodating slot and connecting the corresponding function-expanding interface in the accommodating with the function interface of the electronic device.

Abstract: A system, method, and computer program product are provided for utilizing a data pointer table pre-fetcher. In use, an assembly of a data pointer table within a main memory is identified. Additionally, the data pointer table is pre-fetched from the main memory. Further, data is sampled from the pre-fetched data pointer table. Further still, the sampled data is stored within a data pointer table cache.

Abstract: A system, method, and computer program product for compressing a bounding volume hierarchy is disclosed. The method includes the steps of receiving a bounding volume hierarchy and encoding the bounding volume hierarchy to generate an encoded bounding volume hierarchy, wherein each node in the encoded bounding volume hierarchy indicates whether the node inherits zero or more values from a parent node. The bounding volume hierarchy includes a plurality of nodes, each node in the plurality of nodes is associated with a bounding volume.

Abstract: The present invention provides a printed circuit board (PCB) board, a core for manufacturing the PCB board and a method for manufacturing the PCB board. The PCB board is in a shape of a rectangle and comprises a fiber layer formed of interlacedly weaved fiberglasses, a metal layer affixed onto a surface of the fiber layer, and a pair of differential signal traces formed on the metal layer, wherein extending directions of the fiberglasses lie at acute angles with respect to a length direction of the rectangle, and the pair of differential signal traces extends along a width direction or the length direction of the rectangle. The PCB board can effectively reduce the possibility of the skew distortion during the transmitting process of the differential signal through adjusting the angle between the fiberglasses and the edge of the core without adjusting or redesigning the original circuit layout.

Abstract: A method for testing an integrated circuit to reduce peak power problems during scan capture mode is presented. The method comprises programming a respective duration of a first time window for each of a plurality of cores and a cache on the integrated circuit. It further comprises counting the number of pulses of a first clock signal during the first time window for each of the plurality of cores and the cache. Subsequently, the method comprises staggering capture pulses to the plurality of cores and the cache by generating pulses of a second clock signal for each of the plurality of cores and the cache during a respective second time window, wherein the number of pulses generated is based on the respective number of first clock signal pulses counted for each of the plurality of cores and the cache.

Abstract: A flip-flop and a method of receiving a digital signal from an asynchronous domain. In one embodiment, the flip-flop includes: (1) a first loop coupled to a flip-flop input and having first and second stable states and (2) a second loop coupled to the first loop and having the first and second stable states, properties of cross-coupled inverters in the first and second loops creating a metastable state skewed toward the first stable state in the first loop and skewed toward the second stable state in the second loop. Certain embodiments of the flip-flop have lower time constant and thus a higher Mean Time Between Failure (MTBF).

Abstract: A mechanism for enabling a user to vary the scale or zoom of image data for aspect ratio conversion using a graphical user interface is disclosed. A user may move a selector of the graphical user interface to one end for selecting a linear scaling, to the other end for selecting a parabolic scaling or in between for selecting a scaling associated with another function, thereby enabling a user to vary the magnitude of the scaling across the image data. A parametric function with a single parameter may be used to scale the image data, where the movement of the selector may change the parameter and consequently vary the scaling of the image data. In this manner, a user may efficiently vary or select the scaling of the image data using a graphical user interface to reduce objectionable distortion associated with changing the aspect ratio of the image data.

Abstract: One embodiment of the present invention sets forth a technique for specifying scene programs, where the effect of executing a particular scene program is to generate a sequence of graphics commands. The application programming interface is extended to include calls used to specify a high-level scene program. Upon receiving a high-level scene program, the graphics driver generates a machine code scene program. When an application program emits a call to execute one or more machine code scene programs, the graphics driver transmits corresponding scene programs execution commands to the graphics pre-processing unit. For each scene program execution command, the graphics pre-processing unit processes instructions, programmatically reconfigures the graphics pipeline based on the execution of the machine code scene program, and launches one or more parallel threads that execute commands within the graphics pipeline.

Abstract: A system and method for routing a buffered interconnect in an IC from a source cell to a target cell thereof. In one embodiment, the system includes: (1) a path tracer operable to designate the source cell as a current node and construct a path toward the target node by: (1a) defining a boundary about the current node based on a buffer driving length, (1b) trimming the boundary by any blockage therein to yield a candidate area for placing a buffer, (1c) dividing the boundary into line segments, (1d) selecting a closest, valid one of the line segments to the target cell as the current node and (1e) repeating the defining, trimming, dividing and selecting the closest, valid one until the current node lies within the buffer driving length and (2) a buffer placer associated with the path tracer and operable to select a location along the path to place the buffer.

Abstract: A system and method are provided for test program generation using key enumeration and string replacement. A system includes a test program generator and a tester. The tester receives a test program from the test program generator and tests one or more products according to the test program. The test program generator receives a seed file from a seed file database and a configuration file from a configuration file database. The test program generator iterates over enumeration keys in the configuration file and, for each key, apply to the seed file one or more rules in the configuration file keyed to the enumeration key. Applying a rule includes replacing in the seed file one or more occurrences of a predicate value of the rule with a transformation value of the rule. The test program generator also outputs to the tester the modified first seed file as the test program.

Abstract: A system, method, and computer program product are provided for determining a size of an attribute storage buffer. Input attributes read by a shader program to generate output attributes are identified. A portion of the output attributes to be consumed by a destination shader program is identified. The size of the attribute storage buffer that is allocated for execution of the shader program is computed based on the input attributes and the portion of the output attributes.

Abstract: A flat panel electronic device and an audio playing apparatus thereof are provided. The audio playing apparatus comprises an audio generator, a plurality of speakers, a sensor and a controller. The audio generator is operable to generate a left channel audio and a right channel audio. The plurality of speakers are configured such that at least one pair of speakers is symmetrically disposed at a left side and a right side of the flat panel electronic device no matter how the flat panel electronic device is placed. The sensor is operable to detect a placed state of the flat panel electronic device in the installed state. The controller is operable to receive a detecting signal from the sensor so as to control the at least one pair of speakers to play the left channel audio and the right channel audio correspondingly according to the placed state of the flat panel electronic device.

Abstract: A device for processing graphics data may include a plurality of graphics processing units. The device may include a fan to dissipate thermal energy generated during the operation of the plurality of graphics processing units. Each of the plurality of graphics processing units may generate a pulse width modulated signal to control the speed of the fan. The device may include one or more monitoring units configured to monitor a signal controlling the speed of the fan. One or more of the plurality of pulse width modulated signals may be adjusted based on the monitored signal. One or more of the plurality of pulse width modulated signals may be adjusted such that a signal controlling the fan maintains a desired duty cycle.

Abstract: A method includes determining, through test instructions executing on a processor of a data processing device, utilization of a graphics engine of the processor by an application executing thereon based on initiation thereof through a driver associated with the processor and/or an operating system executing on the data processing device, and detecting, through the test instructions, an idle state of one or more non-graphics engine(s) of the processor. The method also includes transitioning, through the processor, a frame buffer associated therewith into a self-refresh mode of low power utilization thereof, and copying data related to the execution of the application to a memory of the data processing device. Further, the method includes clock-gating the one or more non-graphics engine(s) to reduce a power consumption of the data processing device, and enabling the graphics engine to utilize the copied data in the memory for continued execution of the application.

Abstract: A method and a system are provided for performing address-based memory access assist. An address is received for a memory access and a determination is made, based on the address, that access assist is enabled for at least one storage cell corresponding to the address. The access assist is applied to the at least one storage cell to perform the memory access.

Abstract: A system, method, and computer program product are provided for. The method includes the steps of executing a block of translated binary instructions by multiple threads and gathering profiling data during execution of the block of translated binary instructions. The multiple threads are then synchronized at a barrier instruction associated with the block of translated binary instructions and the block of translated binary instructions is replaced with optimized binary instructions, where the optimized binary instructions are produced based on the profiling data.