Patents Assigned to NVidia
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Patent number: 9209792Abstract: The present invention systems and methods enable configuration of functional components in integrated circuits. In one embodiment clock signal selection system includes an arbitration component, a control component, and a selection component The arbitration component coordinates arbitration eligibility between a plurality of clock signals. The control component controls the coordination utilizing a clock signal from the plurality of clock signals. The selection component selects between the plurality of signals.Type: GrantFiled: August 15, 2007Date of Patent: December 8, 2015Assignee: NVIDIA CORPORATIONInventor: Gary A. Browning
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Patent number: 9208606Abstract: A system, method, and computer program product are provided for extruding an object through a two-dimensional scene. In use, a two-dimensional object is identified within a two-dimensional scene. Additionally, a three-dimensional model is determined that corresponds to the two-dimensional object. Further, the three-dimensional model is extruded through the two-dimensional scene to create a three-dimensional object.Type: GrantFiled: August 22, 2012Date of Patent: December 8, 2015Assignee: NVIDIA CorporationInventor: David R. Cook
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Patent number: 9210437Abstract: A hardware multi-stream multi-standard video decoder device. A command parser accesses a plurality of video streams, identifies a video encoding standard used for encoding video streams of the plurality of video streams, and interleaves portions of the plurality of video streams. A plurality of hardware decoding blocks perform operations associated with decoding the plurality of video streams, wherein different subsets of the plurality of hardware decoding blocks are for decoding video streams encoded using different video encoding standards, such that interleaved video streams are decoded by activating subsets of the plurality of hardware decoding blocks for use in decoding the plurality of video streams. A plurality of register sets store parameters associated with the plurality of video streams.Type: GrantFiled: December 9, 2005Date of Patent: December 8, 2015Assignee: NVIDIA CORPORATIONInventors: Harikrishna M. Reddy, Ignatius B. Tjandrasuwita, Iole Moccagatta
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Patent number: 9208605Abstract: Multisampling techniques provide temporal as well as spatial antialiasing. Coverage for a primitive is determined at multiple sample locations for a pixel. In one embodiment, coverage is determined using boundary equations representing a boundary surface of the primitive in a three-dimensional space-time. A shading value for the primitive is computed for the pixel and stored for each coverage sample location of the pixel that is covered by the primitive. The sample locations are distributed in both space and time, and multiple sample locations share a single shading computation. The multisampling techniques are extendable to other dimensions that correspond to other image attributes.Type: GrantFiled: September 25, 2008Date of Patent: December 8, 2015Assignee: NVIDIA CorporationInventors: Cass W. Everitt, Rui M. Bastos
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Patent number: 9208108Abstract: A system for selecting a subset of issued flash storage commands to improve processing time for command execution. A plurality of ports stores a first plurality of command identifiers and are associated with the plurality of ports. Each of the first plurality of arbiters selects an oldest command identifier among command identifiers within each corresponding port resulting in a second plurality of command identifiers. A second arbiter makes a plurality of selections from the second plurality of command identifiers based on command identifier age and the priority of the port. A session identifier queue stores commands associated with the plurality of selections among other commands forming a third plurality of commands. A microcontroller selects an executable command from the third plurality of commands for execution based on an execution optimization heuristic. After execution of the command, the command identifier in the port is cleared.Type: GrantFiled: December 19, 2008Date of Patent: December 8, 2015Assignee: NVIDIA CORPORATIONInventors: Dmitry Vyshetsky, Howard Tsai, Paul Gyugyi
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Patent number: 9207277Abstract: A wafer acceptance test (WAT) system and method that, in one embodiment, includes: (1) a saturation current WAT subsystem operable to generate a weighted standard deviation based on target NMOS and PMOS saturation currents and saturation current WAT results, (2) a wafer IC speed WAT subsystem operable to generate a speed performance probability distribution of wafer ICs based on the weighted standard deviation and speed WAT results, (3) a wafer IC power WAT subsystem operable to employ the speed WAT results and power WAT results to generate a power performance model of wafer ICs, and (4) a yield calculator operable to generate a power performance variance probability distribution of wafer ICs based on the power performance model and the power WAT results, and to employ the speed performance probability distribution and the power performance variance probability distribution to generate the yield forecast with respect to a target performance profile.Type: GrantFiled: October 30, 2012Date of Patent: December 8, 2015Assignee: NVIDIA CORPORATIONInventors: Craig Nishizaki, Peter Hung, Gunaseelan Ponnuvel, Chien-Hsiung Peng
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Patent number: 9202303Abstract: One embodiment of the present invention sets forth a technique for compositing a rendered path object into an image buffer. A shader program executing within a graphics processing unit (GPU) performs a stenciling operation for the path object and subsequently performs a texture barrier operation, which invalidates caches configured to store texture and frame buffer data within the GPU. The shader program then performs covering operation for the path object in which the shader renders color samples for the path object and composites the color samples into an image buffer. The shader program binds to the image buffer for access as both a texture map and a writeable image. Stencil values are reset when corresponding pixels are written once per path object, and texture caches are invalidated via the texture barrier operation, which is performed after each covering operation per path object.Type: GrantFiled: May 20, 2011Date of Patent: December 1, 2015Assignee: NVIDIA CorporationInventors: Jeffrey A. Bolz, Mark J. Kilgard
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Patent number: 9201670Abstract: A system, method, and computer program product are provided for determining whether parameter configurations meet predetermined criteria. In use, predetermined criteria associated with a software element are identified. Additionally, it is determined whether each of a plurality of different parameter configurations meets the criteria, utilizing a directed acyclic graph (DAG).Type: GrantFiled: July 6, 2012Date of Patent: December 1, 2015Assignee: NVIDIA CorporationInventor: John F. Spitzer
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Patent number: 9204158Abstract: A hardware multi-standard video decoder device. A command parser accesses a video stream and identifies a video encoding standard used for encoding the video stream. A plurality of hardware decoding blocks perform operations associated with decoding the video stream, wherein different subsets of the plurality of hardware decoding blocks are for decoding video streams encoded using different video encoding standards.Type: GrantFiled: December 9, 2005Date of Patent: December 1, 2015Assignee: NVIDIA CORPORATIONInventors: Ignatius B. Tjandrasuwita, Harikrishna M. Reddy, Iole Moccagatta
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Patent number: 9201283Abstract: A display panel is provided that includes a plurality of pixel units, each having a first surface and a second surface opposite to the first surface, and comprising an electrophoretic gel part with a shape tapered in a direction from the first surface to the second surface, wherein a top surface of the electrophoretic gel part forms the first surface and electrophoretic particles are provided in the electrophoretic gel part; a light guiding part with a shape tapered in a direction from the second surface to the first surface, wherein the light guiding part and the electrophoretic glue part match in shape and abut with each other, and a bottom surface of the light guiding part forms at least a portion of the second surface; and a light-emitting device provided on the bottom surface of the light guiding part and operable to emit light toward the first surface.Type: GrantFiled: September 5, 2013Date of Patent: December 1, 2015Assignee: NVIDIA CorporationInventor: Shuang Xu
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Patent number: 9201434Abstract: A system and method are provided for regulating a voltage at a load. A target current is obtained and a number of regulator phases needed to provide the target current to a load is computed based on an efficiency characteristic of the regulator phases. The regulator phases are configured to provide the target current to the load. A multi-phase electric power conversion device comprises at least two regulator phases and a multi-phase control unit. The multi-phase control unit is configured to obtain the target current, compute the number of the regulator phases needed to provide the target current to the load based on the efficiency characteristic of the regulator phases, and configure the regulator phases to provide the target current to the load.Type: GrantFiled: March 1, 2013Date of Patent: December 1, 2015Assignee: NVIDIA CorporationInventor: William J. Dally
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Patent number: 9202139Abstract: A system, method, and computer program product are provided for generating a subset of a low discrepancy sequence. In use, a low discrepancy sequence is identified. Additionally, a threshold value is determined. Further, a single dimension of the low discrepancy sequence is selected. Further still, for each element included within the low discrepancy sequence, the selected single dimension is compared to the determined threshold value. Also, a subset of the low discrepancy sequence is generated, based on the comparing.Type: GrantFiled: May 16, 2013Date of Patent: December 1, 2015Assignee: NVIDIA CorporationInventors: Alexander Keller, Nikolaus Binder
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Patent number: 9204422Abstract: One aspect provides a modem for use at a terminal. The modem comprises a first interface and a processing unit. The first interface is arranged to connect to a communications network. The processing unit is arranged to receive a message from the communications network via the first interface while in an operating mode. The processing unit is also arranged to assess the message on receipt to determine that one or more public warning message is to be broadcast to the modem from the communication network in a second later time period. The processing unit is also arranged to, based on the determination, modify operation of the modem in the second later time period to ensure the one or more public warning message is received and acted on by the modem.Type: GrantFiled: May 21, 2013Date of Patent: December 1, 2015Assignee: NVIDIA CORPORATIONInventor: Alexander May-Weymann
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Publication number: 20150339209Abstract: One embodiment of the present invention includes a dependency extractor and a dependency investigator that, together, facilitate performance analysis of computer systems. In operation, the dependency extractor instruments a software application to generate run-time execution data for each work task. This execution data includes per-task performance data and dependency data reflecting linkages between tasks. After the instrumented software application finishes executing, the dependency investigator evaluates the captured execution data and identifies the critical path of tasks that establishes the overall run-time of the software application. Advantageously, since the execution data includes both task-level performance data and dependencies between tasks, the dependency investigator enables the developer to effectively optimize software and hardware in computer systems that are capable of concurrently executing tasks.Type: ApplicationFiled: May 21, 2014Publication date: November 26, 2015Applicant: NVIDIA CORPORATIONInventors: Andrew Robert KERR, Matthew Grant BOLITHO, Igor SEVASTIYANOV, Scott RICKETTS, Michael ANDERSCH
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Patent number: 9195434Abstract: A true random number generator, a method of generating a true random number and a system incorporating the generator or the method. In one embodiment, the generator includes: (1) a ring oscillator including inverting gates having power inputs and (2) a time-varying power supply coupled to the power inputs to provide power thereto and including power perturbation circuitry operable to perturb the power provided to at least one of the power inputs.Type: GrantFiled: January 14, 2014Date of Patent: November 24, 2015Assignee: Nvidia CorporationInventor: Sachin Idgunji
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Patent number: 9195460Abstract: Systems and methods for compiling programs using condition codes and executing those programs when non-numeric values are present allow for explicit handling of non-numeric values. In addition to the conventional condition code values of positive, negative, and zero, a fourth value may be encoded, not a number (NaN) representing a non-numeric value. New condition tests are defined that explicitly account for condition code values of NaN. A compiler may produce code using the new condition tests to represent if and if-else statements. The code including the new condition tests generates deterministic results during execution when non-numeric values are present.Type: GrantFiled: May 2, 2006Date of Patent: November 24, 2015Assignee: NVIDIA CORPORATIONInventors: Robert Steven Glanville, John Erik Lindholm, Ming Y. Siu
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Patent number: 9197365Abstract: Method, receiver and computer program product for decoding a coded data block received at the receiver are disclosed. A first plurality of coded data bits representing the coded data block are received. First soft information values are determined corresponding to respective ones of the received first plurality of coded data bits, wherein each of the soft information values indicates a likelihood of a corresponding coded data bit having a particular value. An attempt is made to decode the coded data block using the first soft information values. The first soft information values are compressed. The compressed first soft information values are stored in a data store. A second plurality of coded data bits representing the coded data block is received and second soft information values corresponding to respective ones of the received second plurality of coded data bits are determined. The compressed first soft information values are retrieved from the data store and decompressed.Type: GrantFiled: September 25, 2012Date of Patent: November 24, 2015Assignee: NVIDIA CORPORATIONInventors: Stephen Felix, Dinkar Vasudevan, Steve Allpress
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Patent number: 9195269Abstract: A roll compensation system for an electronic device, a method of mitigating impact of an electronic device and an impact-resistant mobile device incorporating the system or the method. In one embodiment, the system includes: (1) a plurality of sensors operable to detect orientation and motion of the electronic device, (2) a controller configured to detect a fall based on the motion and determine a mitigating roll based on the orientation and the motion and (3) a compensator operable to carry out the mitigating roll thereby reducing the probability of a catastrophic impact.Type: GrantFiled: March 27, 2013Date of Patent: November 24, 2015Assignee: Nvidia CorporationInventor: Daniel Rohrer
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Patent number: 9195618Abstract: A system for selecting memory requests. The system includes arbiters and a time ordered list scheduler. Each arbiter selects a memory request for transmission from at least one client. The scheduler is operable to receive and store memory requests from the arbiters and selects a selected memory request for forwarding to a memory system. The scheduler includes a list structure operable to store memory requests received from the arbiters in a fashion to preserve relative time of arrival of the memory requests. The scheduler includes scanners that are prioritized with respect to one another. Scanners are operable to simultaneously scan contents of the list structure from the oldest to newest requests and determine whether a memory request match is found based on associated programmable rules to locate a memory request candidate. A memory request candidate of a highest priority scanner is selected by the scheduler as the selected memory request.Type: GrantFiled: June 16, 2009Date of Patent: November 24, 2015Assignee: NVIDIA CORPORATIONInventor: Roger Eckert
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Patent number: 9198123Abstract: A modem is disclosed, one embodiment including: first and second interface apparatuses; and a processing apparatus arranged to transmit a request message to part of a wireless cellular network to request establishment of a channel to access a packet-based network, wherein the request message requests the channel as being of a type that supports both a first and second version of a packet protocol; receive a response message indicating rejection of the request, and upon detecting that a field in the response message defines a reason other than the part of the wireless cellular network does not support first and second versions of the packet protocol on a single channel, to default to transmit a default request message to request establishment of a channel to access the packet-based network, the default request message requests the channel as being of a type that supports the first version of the packet protocol.Type: GrantFiled: January 30, 2013Date of Patent: November 24, 2015Assignee: Nvidia CorporationInventors: Flavien Delorme, Bruno De Smet