Patents Assigned to NVidia
  • Patent number: 9147270
    Abstract: A method for reducing the number of samples tested for rendering a screen space region of an image includes constructing a trajectory of a primitive in a three dimensional coordinate system, the coordinate system including a screen space dimension, a lens dimension and a time dimension. A bounding volume is constructed for a screen space region which is to be rendered, the bounding volume overlapping a portion of the screen space region. The bounding volume is defined according to a plurality of bounding planes which extend in the three dimensional coordinate system, whereby the bounding planes are determined as a function of the trajectory of the primitive. One or more sample points which are located within the screen space region, and which are not overlapped by the bounding volume are excluded from testing.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: September 29, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Jaakko Lehtinen, Timo Aila, Samuli Laine
  • Patent number: 9147224
    Abstract: One embodiment of the present invention sets forth a technique for receiving versions of state objects at one or more stages in a processing pipeline. The method includes receiving a first version of a state object at a first stage in the processing pipeline, determining that the first version of the state object is relevant to the first stage, incrementing a first reference counter associated with the first version of the state object, assigning the first version of the state object to work requests that arrive at the first stage subsequent to the receipt of the first version of the state object, and transmitting the first version of the state object to a second stage in the processing pipeline.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: September 29, 2015
    Assignee: NVIDIA Corporation
    Inventors: Sean J. Treichler, Lacky V. Shah, Daniel Elliot Wexler
  • Patent number: 9147264
    Abstract: A method for performing image rendering. The method includes identifying a tile in an image, wherein the image comprises a plurality of tiles including color data that is displayed by a plurality of pixels. A quantized first base value and a quantized second base value are accessed from a block of memory, wherein the block is associated with the tile. Reverse quantization is performed on the quantized first and second base values to obtain a reproduced first base value, and a reproduced second base value corresponding to the tile for purposes of determining color values for corresponding pixels.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: September 29, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Walter E. Donovan, Tyson J. Bergland
  • Patent number: 9148544
    Abstract: A system, process, and computer program product are provided for scanning a document with a hand-held device. An approach for scanning the document includes the steps of sampling one or more values from an array of sensors integrated into a hand-held device, determining whether the device has moved at least a threshold distance, and sampling one or more additional values from the array of sensors.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: September 29, 2015
    Assignee: NVIDIA Corporation
    Inventors: Dhaval Sanjaykumar Dave, Anup Ashok Dalvi
  • Patent number: 9146949
    Abstract: Described are data structures and methodology for forming same, for network protocol processing. A method for creating data structures for firewalling and network address translating is described. A method for creating data structures for physical layer addressing is described. A method for security protocol support using a data structure is described. A method for creating at least one data structure sized responsive to whether a firewall is activated is described. A data structure for routing packets is described. A method of forming hashing table chains is described. A method and apparatus for tracking packet states is described. More particularly, Transmission Control Protocol (“TCP”) tracking of states for packets is described. In an embodiment, a division between software states and hardware states is made as a packet is processed by both software and hardware. A method and apparatus for network protocol processing are also described.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: September 29, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Thomas A. Maufer, Paul J. Gyugl, Sameer Nanda, Paul J. Sidenblad
  • Patent number: 9142040
    Abstract: A system, method, and computer program product are provided for processing graphics data associated with shading. In operation, a first fragment is received. Further, the first fragment is shaded. While the first fragment is being shaded, a second fragment is received and it is determined whether at least one aspect of the second fragment conflicts with the first fragment. If it is determined that the at least one aspect of the second fragment does not conflict with the first fragment, the second fragment is shaded. If it is determined that the at least one aspect of the second fragment conflicts with the first fragment, information associated with the second fragment is stored, a third fragment is received, and the third fragment is shaded, if it is determined that at least one aspect of the third fragment does not conflict with the first fragment.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 22, 2015
    Assignee: NVIDIA Corporation
    Inventors: Emmett M. Kilgariff, Tyson Bergland, Dale L. Kirkland, Rui Manuel Bastos, Christian Jean Rouet
  • Patent number: 9142005
    Abstract: One embodiment of the present invention sets forth a technique for placing texture barrier instructions within a thread program to advantageously enable efficient and correct operation of the thread program. A thread program compiler statically determines a pending request count needed to progress beyond a particular texture barrier instruction, which blocks execution of subsequent instructions that depend on previously requested data. Each instance of the thread program blocks execution at the barrier instruction until a pending request count condition is satisfied. This technique may advantageously reduce power consumption in a graphics processing unit by eliminating power consumption associated with conventional, generalized scoreboard resources.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: September 22, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Maxim Lukyanov, Boris Beylin, Robert Steven Glanville, Alexander Grosul
  • Patent number: 9142043
    Abstract: A method for reducing the number of samples tested for rendering a screen space region of an image includes constructing a trajectory of a primitive extending within an image which is to be rendered. A bounding volume is constructed for a screen space region of the image, the bounding volume characterized as having a bound in a non-screen space dimension which is defined as a function of the primitive's trajectory. The bounding volume is further characterized as overlapping a portion of the screen space region which is to be rendered. One or more sample points which are located within the screen space region, and which are not overlapped by the bounding volume are excluded from testing.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: September 22, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Timo Aila, Samuli Laine, Tero Karras, Jaakko Lehtinen, Peter Shirley
  • Patent number: 9143244
    Abstract: A method of mitigating interference between carrier frequency bands of a carrier aggregation scheme. The method comprises: at a wireless device, receiving a first signal on a first carrier frequency band of the carrier aggregation scheme; mixing a second signal onto a second carrier frequency band of the carrier aggregation scheme and transmitting the second signal from the wireless device; executing code on a processing apparatus of the device to generate a reconstructed interference signal, by mixing an instance of the signal with a frequency location of an interfering harmonic from the second carrier frequency band falling in the first carrier frequency band; and removing the reconstructed interference signal from the first signal.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: September 22, 2015
    Assignee: Nvidia Corporation
    Inventor: Stephen A. Allpress
  • Patent number: 9135081
    Abstract: One embodiment of the present invention enables threads executing on a processor to locally generate and execute work within that processor by way of work queues and command blocks. A device driver, as an initialization procedure for establishing memory objects that enable the threads to locally generate and execute work, generates a work queue, and sets a GP_GET pointer of the work queue to the first entry in the work queue. The device driver also, during the initialization procedure, sets a GP_PUT pointer of the work queue to the last free entry included in the work queue, thereby establishing a range of entries in the work queue into which new work generated by the threads can be loaded and subsequently executed by the processor. The threads then populate command blocks with generated work and point entries in the work queue to the command blocks to effect processor execution of the work stored in the command blocks.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: September 15, 2015
    Assignee: NVIDIA Corporation
    Inventors: Ignacio Llamas, Craig Ross Duttweiler, Jeffrey A. Bolz, Daniel Elliot Wexler
  • Patent number: 9135675
    Abstract: Systems and methods for utilizing multiple graphics processing units for controlling presentations on a display are presented. In one embodiment, a dual graphics processing system includes a first graphics processing unit for processing graphics information; a second graphics processing unit for processing graphics information; a component for synchronizing transmission of display component information from the first graphics processing unit and the second graphics processing unit and a component for controlling switching between said first graphics processing unit and said second graphics processing unit. In one embodiment, the component for synchronizing transmission of display component information adjusts (e.g., delays, speeds up, etc.) the occurrence or duration of a corresponding graphics presentation characteristic (e.g., end of frame, end of line, vertical blanking period, horizontal blanking period, etc.) in signals from multiple graphics processing units.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: September 15, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: David Wyatt, Manish Modi
  • Patent number: 9134979
    Abstract: A basic block within a thread program is characterized for convergence based on mapping the basic block to an indicator subnet within a corresponding Petri net generated to model the thread program. Each block within the thread program may be similarly characterized. Each corresponding Petri net is enumerated to generate a corresponding state space graph. If the state space graph includes an exit node with an odd execution count attribute, such as by Petri net coloring, then the corresponding basic block is divergent. The corresponding basic block is convergent otherwise. Using this characterization technique, a thread program compiler may advantageously identify all convergent blocks within a thread program and apply appropriate optimizations to the convergent blocks.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: September 15, 2015
    Assignee: NVIDIA Corporation
    Inventor: Manjunath Kudlur
  • Patent number: 9135214
    Abstract: A system, method, and computer program product are provided for assigning elements of a matrix to processing threads. In use, a matrix is received to be processed by a parallel processing architecture. Such parallel processing architecture includes a plurality of processors each capable of processing a plurality of threads. Elements of the matrix are assigned to each of the threads for processing, utilizing an algorithm that increases a contiguousness of the elements being processed by each thread.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: September 15, 2015
    Assignee: NVIDIA Corporation
    Inventors: William N. Bell, Michael J. Garland
  • Patent number: 9134782
    Abstract: Power supply voltage to an integrated circuit (IC) or a portion of an IC is maintained at an optimum level matching the IC performance. Voltage ranges and delay measures for corresponding operating frequencies are stored in tables in a voltage control block. When a new frequency of operation is desired, the voltage control block measures delay performance of the IC, and sets the supply voltage to a value specified in a corresponding entry in a table. The voltage control block then continues to measure delay performance, and dynamically adjusts the power supply voltage to an optimum value thereby minimizing power consumption.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: September 15, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Sreenivas Aerra Reddy, Srinivasan Arulanandam, Venkataraman Rajaraman
  • Patent number: 9134787
    Abstract: To preserve power and increase the overall efficiency of the CPU, the platform idle driver causes the power gate controller to cut power to the idle core. Such power gating is autonomous, i.e., the operating system and the other cores are not involved. In operation, the platform idle driver first prepares the core and the power gate controller for power gating the core. The platform idle driver then triggers the power gating. The power gate controller monitors interrupts released by the interrupt controller, and if any on the released interrupts are associated with the power gated core, the power gate controller resumes dispersing power to the core.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: September 15, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Matthew Raymond Longnecker, Scott Alan Williams, Sagheer Ahmad, Robert Alan Bignell, Venkata Krishna Reddy Dumpa
  • Patent number: 9135369
    Abstract: A system, method, and computer program product are provided for performing graph aggregation. In use, a graph with a plurality of vertices and a plurality of edges is identified. Additionally, aggregation is performed on the vertices and edges of the graph by computing a graph matching, where such graph matching is performed in a data-parallel manner.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: September 15, 2015
    Assignee: NVIDIA Corporation
    Inventors: Patrice Castonguay, Jonathan Michael Cohen
  • Publication number: 20150255365
    Abstract: A microelectronic package includes a package substrate with at least one semiconductor die mounted thereon and a plate coupled to the package substrate. The plate is configured with a first recess formed in a first edge of the plate and a second recess formed in a second edge of the plate wherein the first edge and the second edge are formed on opposing sides of the plate. One advantage of the above-described embodiments is that a stiffener plate or heat spreader that is sized to cover most or all of the periphery of a package substrate can be coupled to the package substrate without causing alignment issues in subsequent fabrication processes.
    Type: Application
    Filed: March 5, 2014
    Publication date: September 10, 2015
    Applicant: NVIDIA CORPORATION
    Inventors: Yeong J. LEE, Ernie OPINIANO
  • Publication number: 20150253373
    Abstract: Dynamic yield prediction. In accordance with a first method embodiment of the present invention, a computer-implemented method includes collecting sample test information from a plurality of test-only structures prior to completion of the first wafer, gathering finished test data from all die of the first wafer, after completion of the first wafer, constructing a yield prediction model based on the sample test information and on the finished test data, and predicting, using the model, a percentage of die of the first wafer that will meet a particular specification. The method may further include a feedback loop to dynamically update the model.
    Type: Application
    Filed: March 4, 2014
    Publication date: September 10, 2015
    Applicant: NVIDIA Corporation
    Inventors: Nicholas CALLEGARI, Bruce CORY, Joe GRECO
  • Patent number: 9131445
    Abstract: In an aspect there is provided a method of moving a processor of a mobile device from a low-power state for conserving power to an active mode for processing signals. The mobile device is configured to receive regularly scheduled signals. The method comprises, for each of multiple operating states of the mobile device determining a restore time associated with the operating state of the mobile device and storing each determined restore time in association with its operating state. The method further comprises detecting a current operating state of the mobile device and using the determined restore time for that state to set a trigger time to control movement of the processor of the mobile device to enter the active mode from the low-power mode in time to process the scheduled signals.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: September 8, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Greg Heinrich, Robert Riglar
  • Patent number: 9129443
    Abstract: A cache-efficient processor and method for rendering indirect illumination using interleaving and sub-image blur. One embodiment of the processor is configured to render an indirect illumination image and includes: (1) a buffer restructurer configured to organize a reflective shadow map (RSM), rendered with respect to a reference point, into a plurality of unique sub-RSMs, each having sub-RSM pixels, (2) an indirect illumination computer configured to employ interleaved sampling on the plurality of unique sub-RSMs to generate a plurality of indirect illumination sub-images, and (3) a filter operable to smooth accumulated light values of the indirect illumination sub-images for subsequent interleaving into the indirect illumination image.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: September 8, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Holger Gruen, Louis Bavoil