Patents Assigned to NVidia
  • Patent number: 9123173
    Abstract: In a raster stage of a graphics pipeline, a method for rasterizing non-rectangular tile groups. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor. The graphics primitive is rasterized at a first level by generating a non-rectangular footprint comprising a set of pixels related to the graphics primitive. The graphics primitive is then rasterized at a second level by accessing the set of pixels and determining covered pixels out of the set of pixels. The raster stage subsequently outputs the covered pixels for rendering operations in a subsequent stage of the graphics processor.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: September 1, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Justin S. Legakis, Franklin C. Crow, John S. Montrym, Douglas A. Voorhies
  • Patent number: 9122643
    Abstract: Methods and systems of initiating a backup process of data stored on a computer are described. One method calls for the data to be backed up to be identified. A backup event trigger is defined, and the computer is monitored for the occurrence of the backup event trigger. If the trigger occurs, a balancing heuristic is applied, to determine whether to initiate the backup process.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: September 1, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: William Samuel Herz, Andrew C. Fear
  • Patent number: 9123438
    Abstract: A configurable delay circuit and a method of clock buffering. One embodiment of the configurable delay circuit includes: (1) a first delay stage electrically couplable in series to a second delay stage, the first delay stage and the second delay stage each having an input port electrically coupled to a signal source, and (2) a delay path select circuit electrically coupled between the first delay stage and the second delay stage, and operable to select between a delay path including the first delay stage and another delay path including the first delay stage and the second delay stage.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: September 1, 2015
    Assignee: Nvidia Corporation
    Inventors: Hwong-Kwo Lin, Lei Wang, Spencer Gold, Zhenye Jiang
  • Patent number: 9123128
    Abstract: Employing a general processing unit as a programmable function unit of a graphics pipeline and a method of manufacturing a graphics processing unit are disclosed. In one embodiment, the graphics pipeline includes: (1) accelerators, (2) an input output interface coupled to each of the accelerators and (3) a general processing unit coupled to the input output interface and configured as a programmable function unit of the graphics pipeline, the general processing unit configured to issue vector instructions via the input output interface to vector data paths for the programmable function unit.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: September 1, 2015
    Assignee: Nvidia Corporation
    Inventor: Albert Meixner
  • Publication number: 20150241976
    Abstract: Systems and methods for remotely providing user input to different electronic devices based on user finger motions and/or gestures. A universal user input device assembles a motion sensor, control logic, a memory and a processor into a substantially ring-shaped housing that is wearable on a finger of a user. The input device can identify an associated external device, establish a communication channel therewith, and provide user input instructions to the external device based on user's finger motions or gestures. The motion sensor can detect the finger's motions and/or gestures and generate corresponding detection signals which are converted into instruction signals recognizable by the external device. The instruction signals are communicated to the external device through a wireless communication channel. The input device may include a projector that can optically project a graphic user interface to an external surface as a visual guide for user's finger motions or gestures.
    Type: Application
    Filed: February 21, 2014
    Publication date: August 27, 2015
    Applicant: NVIDIA Corporation
    Inventors: Yu ZHAO, Xiang SUN, Fei WANG
  • Publication number: 20150243048
    Abstract: A system, method, and computer program product are provided for implementing a search of a digital image along a set of paths. The method includes the steps of selecting a set of paths in an image and identifying at least one feature pixel in the set of paths by comparing gradients for each of the pixels in the set of paths. The set of paths includes at least one line of pixels in the image, and a total number of pixels in the set of paths is less than half of a number of pixels in the image.
    Type: Application
    Filed: February 26, 2014
    Publication date: August 27, 2015
    Applicant: NVIDIA Corporation
    Inventors: Kihwan Kim, Dawid Stanislaw Pajak, Kari Antero Pulli
  • Publication number: 20150243233
    Abstract: A method for driving a display panel having a variable refresh rate is disclosed. The method comprises receiving a current input frame from an image source. Next, it comprises determining a number of re-scanned frames to insert between the current input frame and a subsequent input frame, wherein the re-scanned frames repeat the input frame, and wherein the number of re-scanned frames depends on the minimum refresh interval (MRI) of the display panel. Further, it comprises calculating respective intervals at which to insert the re-scanned frames between the current input frame and the subsequent input frame. Subsequently, it comprises determining if a charge accumulation in pixels of the display panel has crossed over a predetermined threshold value. Finally, responsive to a determination that the charge accumulation has crossed over a predetermined threshold value, it comprises performing a counter-measure to remediate the charge accumulation.
    Type: Application
    Filed: February 26, 2014
    Publication date: August 27, 2015
    Applicant: NVIDIA Corporation
    Inventors: Rudolf BLOKS, Robert SCHUTTEN, Tom VERBEURE
  • Publication number: 20150243610
    Abstract: A system, method, and computer program product are provided for producing a high bandwidth bottom package of a die-on-package structure. The method includes the steps of receiving a bottom package comprising a substrate material having a top layer and an integrated circuit die that is coupled to the top layer of the substrate material. A first set of pads is formed on the top layer of the substrate material and a layer of dielectric material is applied on a top surface of the bottom package to cover the integrated circuit die and the first set of pads.
    Type: Application
    Filed: February 26, 2014
    Publication date: August 27, 2015
    Applicant: NVIDIA Corporation
    Inventor: Leilei Zhang
  • Patent number: 9118992
    Abstract: One embodiment of the present invention sets forth a system that includes a detection device and a processor. The detection device is configured to sense that a handheld device has not been placed on or near a surface. In response to sensing that the handheld device has not been placed on or near a surface, the detection device is configured to transmit an indicator to the processor. The processor is configured to receive a first audio signal, and determine that the handheld device has not been placed on or near a surface by receiving the indicator from the detection device. In response to determining that the handheld device has not been placed on or near a surface, the processor is further configured to apply a compensating function to the first audio signal to generate a second audio signal, and transmit the second audio signal to a speaker.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: August 25, 2015
    Assignee: NVIDIA Corporation
    Inventors: Nikhil Satish, David Dignam
  • Patent number: 9115721
    Abstract: The present invention provides a turbofan and a graphics card with the turbofan. The turbofan comprises: a turbofan assembly which admits air in an axial direction and dispenses air in a radial direction; an inlet fan assembly disposed at an inlet of the turbofan assembly and disposed coaxially with the turbofan assembly; and a driving means for driving the turbofan assembly and the inlet fan assembly to rotate. The turbofan provided by the invention gathers the ambient air to the inlet through the inlet fan assembly disposed at the inlet of the turbofan assembly, so as to change a negative pressure state at the inlet. Consequently, the cooling efficiency of the turbofan is improved effectively and the noise of the turbofan is reduced.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: August 25, 2015
    Assignee: NVIDIA Corporation
    Inventors: Pengwei Xu, Yuan Yuan, Songliang Ni
  • Patent number: 9118927
    Abstract: Reducing computational complexity when generating sub-pixel values for sub-pixel motion estimation from integer pixels. In an embodiment, half pixels in vertical and horizontal directions are computed by a applying a filter of first complexity on integer pixels, and a half pixel in diagonal direction is computed using a filter of lower complexity as compared to the filter of first complexity. Quarter (and other lower resolution pixels) pixels may also be generated using the half pixel in the diagonal direction. Thus, overall computational complexity is reduced in generating sub-pixels for sub-pixel motion estimation.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: August 25, 2015
    Assignee: NVIDIA CORPORATION
    Inventor: Anurag Goel
  • Patent number: 9117284
    Abstract: An asynchronous computing and rendering system includes a data storage unit that provides storage for processing a large-scale data set organized in accordance to data subregions and a computing cluster containing a parallel plurality of asynchronous computing machines that provide compute results based on the data subregions. The asynchronous computing and rendering system also includes a rendering cluster containing a parallel multiplicity of asynchronous rendering machines coupled to the asynchronous computing machines, wherein each rendering machine renders a subset of the data subregions. Additionally, the asynchronous computing and rendering system includes a data interpretation platform coupled to the asynchronous rendering machines that provides user interaction and rendered viewing capabilities for the large-scale data set. An asynchronous computing and rendering method is also provided.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: August 25, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Marc Nienhaus, Joerg Mensmann, Hitoshi Yamauchi
  • Patent number: 9117309
    Abstract: A method for rendering polygons with a bounding box and a graphics processor unit. The method includes generating a bounding rectangle, wherein each edge of the bounding rectangle is defined to a sub-pixel precision. At least one polygon within the bounding rectangle is cropped to the sub-pixel precision. The polygon is blended with a background color outside the bounding rectangle to anti-alias the polygon with the background color, wherein the blending is performed with the sub-pixel precision of the bounding rectangle.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: August 25, 2015
    Assignee: NVIDIA CORPORATION
    Inventor: Franklin C. Crow
  • Patent number: 9118932
    Abstract: A method includes determining, through a processor and/or a hardware engine, edge pixels and flat pixels of a video frame of a video sequence during decoding thereof or post-processing associated with the decoding based on a predetermined threshold, and quantifying spatial correlation of pixels of the video frame around edges thereof to estimate strength of ringing artifacts and spatial and temporal persistence thereof across the video frame and across video frames of the video sequence. The method also includes adaptively and spatially filtering the pixels around the edges of the video frame, adaptively and temporally filtering the video frame, and blending an output of the adaptive spatial filtering and the adaptive temporal filtering to generate an output with suppressed ringing artifacts, spatial and temporal persistence thereof and artifacts resulting from the cumulative effect of compression therein.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: August 25, 2015
    Assignee: NVIDIA Corporation
    Inventors: Niranjan Avadhanam, Ravi Kumar Boddeti
  • Patent number: 9116668
    Abstract: The present invention provides a panel protecting device of a flat panel electronic device and a flat panel electronic device. The panel protecting device comprises: a sensor for detecting one or more of a falling speed, a falling time and a falling distance of the flat panel electronic device in a vertical direction when the flat panel electronic device is only under gravity; and a protecting means for being mounted around a panel of the flat panel electronic device. The protecting means has a rest position and a protruding position. The protecting means is accommodated in a recess of the flat panel electronic device when the protecting means is in the rest position and protrudes from the panel when the protecting means is in the protruding position. The protecting means moves to the protruding position from the rest position automatically when the one or more of the falling speed, the falling time and the falling distance is greater than or equal to a predetermined value.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: August 25, 2015
    Assignee: NVIDIA Corporation
    Inventors: Cai Xiaozhuo, Yan Shuanghu
  • Patent number: 9117254
    Abstract: A system, method, and computer program product are provided for performing ray tracing. In use, ray tracing is performed utilizing a divide and conquer method, where the divide and conquer method is associated with a cache.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: August 25, 2015
    Assignee: NVIDIA Corporation
    Inventors: Nikolaus Binder, Carsten Alexander Wachter, Alexander Keller
  • Patent number: 9117392
    Abstract: A method includes providing an Input/Output (I/O) interface at a periphery of a motherboard of a data processing device, and providing traces between a processor of the data processing device and the I/O interface across a surface of the motherboard. The traces provide conductive pathways between circuits of the processor and the I/O interface. The method also includes exposing the I/O interface through an external cosmetic surface of the data processing device in an assembled state thereof by way of a port complementary to that of a port of an external graphics card to enable direct coupling of the external graphics card to the data processing device through the exposed I/O interface by way of the complementary ports to provide boosting of processing through the data processing device.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: August 25, 2015
    Assignee: NVIDIA Corporation
    Inventors: Mahesh Sambhaji Jadhav, Rupesh Deorao Chirde
  • Publication number: 20150235681
    Abstract: A memory read system includes a memory column having a plurality of dual port memory cells that are controlled by separate read word lines and a read bit line structure organized into upper and lower read bit line portions. Additionally, the memory read system also includes a pseudo-differential memory read unit coupled to the read bit line structure, wherein the upper and lower read bit line portions respectively control corresponding upper and lower local bit lines to provide a global bit line for the memory column. A method of reading a memory is also included.
    Type: Application
    Filed: May 16, 2014
    Publication date: August 20, 2015
    Applicant: Nvidia Corporation
    Inventors: Gang Chen, Jing Guo, Yiqi Wang, Hwong-Kwo Lin
  • Publication number: 20150235695
    Abstract: A write-assist memory includes a memory supply voltage and a column of SRAM cells that is controlled by a pair of bit lines, during a write operation. Additionally, the write-assist memory includes a write-assist unit that is coupled to the memory supply voltage and the column of SRAM cells and has a separable conductive line located between the pair of bit lines that provides a collapsible SRAM supply voltage to the column of SRAM cells based on a capacitive coupling of a control signal in the pair of bit lines, during the write operation. A method of operating a write-assist memory is also provided.
    Type: Application
    Filed: May 20, 2014
    Publication date: August 20, 2015
    Applicant: Nvidia Corporation
    Inventors: Gang Chen, Jing Guo, Jun Yang
  • Publication number: 20150234963
    Abstract: A method for performing an interface analysis. The method includes identifying a first module included in a representation of a digital circuit. The method also includes identifying a first output port associated with the first module. The method further includes identifying a first logic path that extends from the first output port. The method also includes determining that the first logic path extends to a first storage element included in the first module. The method further includes including the first module, the first output port, the first logic path, and the first storage element in interface logic output data.
    Type: Application
    Filed: February 18, 2014
    Publication date: August 20, 2015
    Applicant: NVIDIA CORPORATION
    Inventors: David Lyndell BROWN, Yi ZHANG